1 Adaptive Raytracing Implementation using Partial Dynamic Reconfiguration Gianluca Durelli 1 , Fabrizio Spada 1 , Riccardo Cattaneo 1 , Christian Pilato 2 , Danilo Pau 3 , Marco D. Santambrogio 1 1 Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Milano, Italy, fabrizio.spada@mail.polimi.it, {durelli,rcattaneo,santambr}@elet.polimi.it 2 Columbia University, Department of Computer Science, New York, NY, USA, pilato@cs.columbia.edu 3 ST Microelectronics, Milano, Italy, danilo.pau@st.com Abstract—The continuous strive for improvements in visual realism is progressively increasing the complexity of algorithms for simulating light physics to produce very realistic scenes. As a result, they are becoming more and more suitable for hardware acceleration, even if they introduce new challenges due to the high requirements in terms of resources. In this paper we propose a hardware implementation of the raytracing algorithm, which is a method for rendering 3D scenes. We exploit partial dynamic reconfiguration to adapt the hardware to the specific part of the image under analysis. This allows us to obtain up to 30% better performance with respect to the software baseline implementation on the AVNET ZedBoard platform. Index Terms—Field Programmable Gate Arrays, Embedded software, Image processing I. I NTRODUCTION The problem of performing 3D rendering in an effective way is becoming more and more important due to the continuous strive for realistic images, as for instance in both movies and video games industries over the recent years. The complexity of simulating light behavior makes these algorithms very computational intensive; for this reason, their implementations are generally carried out exploiting Graphical Processing Units (GPUs) or high-end General Purpose Processors. Harwdare acceleration has been also investigated, especially for Field- Programmable Gate Arrays (FPGAs), at the penality of a huge amount of resources needed to implement the application. On the other hand, Partial Dynamic Reconfiguration (PDR) [1] is a promising technique to cope with limited resources, but it requires the designer to have a high expertise to create the final system. Raytracing is one of these algorithms for 3D scenes render- ing which is able to simulate the physics of a light ray and thus can generate realistic results. The classical implementation of the raytracing algorithm consists in defining a rendering point in a 3D scene and shooting light rays from that point, simulating their reflections and refractions when these rays intersect objects in the scene. The objects are described as a composition of geometric primitives (2D or 3D) such as triangles, polygons, spheres, cones or other shapes. It is clear that the computational complexity of a rendering scene is proportional to the number and the nature of these primitives, along with their positions in the scene itself. Recently progress in High Level Synthesis (HLS) improved the programmability of FPGAs, extending the range of design- ers able to exploit such devices as accelerators for specific application tasks. As an example of these HLS tools, we can mention both academic ones (e.g. GAUT [2], LegUp [3], DWARV [4], bambu [5]) and commercial ones (e.g. Xilinx’s Vivado HLS [6], Cadence’s C-to-Silicon [7], Forte’s Cynthe- sizer [8]). This paper proposes an implementation of the raytracing algorithm for a heterogeneous platform composed of an ARM processor and an FPGA. We adopt Xilinx Vivado HLS to realize the hardware cores and the corresponding interfaces for the integration with the rest of the system, based on the standard AXI bus. The proposed implementation exploits the partial dynamic reconfiguration capability of such device to adapt at run-time the hardware configuration of the board to speed up the computation in specific parts of the input scene, based on the nature of the primitives. A simple policy is proposed to adapt the hardware to a single block under analysis. This adaptation is done by monitoring, at run-time, which the most used primitives at a certain moment and then by configuring the hardware accordingly. The remainder of the paper presents the related work in the area (Section II), the general description of the algorithm and the modification we apported (Section III), the implementa- tion details about the hardware architecture (Section IV), the description of the adaptation policy (Section V), a discussion on the obtained results (Section VI), and finally presents the conclusions introducing possible future extensions of the work (Section VII). II. RELATED WORK The raytracing algorithm has been widely studied over the recent years due to its great interest in computer graphics; this technique can be, indeed, used in rendering of images for