International Journal of Modern Engineering Research (IJMER) www.ijmer.com Vol.3, Issue.3, May-June. 2013 pp-1372-1376 ISSN: 2249-6645 www.ijmer.com 1372 | Page K. Pitambar Patra, 1 Saket Shrivastava, 2 Snehlata Sahu, 3 Sujit Kumar Patel 4 1234 Department of Electronics & Communication Engineering Jaypee University of Engineering & Technology, Guna Abstract: In this paper area-power efficient modulo 2 n +1 multiplier is proposed. The result and one operand for the new modulo multipliers use weighted representation, while the other uses the diminished- 1. By using the radix-4 Booth recoding, the new multipliers reduce the number of the partial products to n/2 for even and (n+1)/2 for odd except for one correction term. According to our algorithm, the resulting partial products are added through inverted end around carry save adder into two operands, which are finally adder by a 2-stage n-bit adder containing 2:1 multiplexer. By using the purposed adder, the new multipliers reduce the area and power. The analytical and experimental result indicates that the new modulo 2 n +1 multipliers, offer reduced power and more compact area among all the existing structures. Keywords: 2-Stage n-Bit Adder, Modulo Multiplier, Residue Number System (RNS). I. INTRODUCTION Residue number systems (RNS) reduce the delay of carries propagation, thus suitable for the implementation of high-speed digital signal processing devices. Some arithmetic operations, such as addition and multiplication, can be carried out more efficiently in RNS than in conventional two’s complement systems. RNS has been adopted in the design of Digital Signal Processors (DSP), Finite Impulse Response (FIR) filters], image processing units, Discrete Cosine Transform (DCT) processors, communication components, cryptography, and other DSP applications . In recent years, efficient schemes for modulo multipliers have been studied intensively. Generally, modulo 2 n +1 multipliers can be divided into three categories, depending on the type of operands that they accept and output: i. the result and both inputs use weighted representation; ii. the result and both inputs use diminished-1 representation; iii. The result and one input use weighted representation, while the other input uses diminished-1. For the first category, Zimmermann et al. [1] used Booth encoding to realize, but depart from the diminished-1 arithmetic, which leads to a complex architecture with large area and delay requirements. For the second category, Wang et al. [2] proposed diminished-1 multipliers with -bit input operands. The multipliers use a non-Booth recoding and a zero partial-product counting circuit. The main drawback in this architecture was handling of zero inputs and results were not considered. Curiger et al. [3] proposed new modulo multipliers by using the third category. This architecture use ROM based look-up methods are competitive. The main drawback in this architecture increasing n-bit, they become infeasible due to excessive memory requirements. Jian et al. [4] also proposed for the third category architecture and reduce the memory requirement and speed up. The new architecture is based on n-bit addition and radix-4 booth algorithm, which is efficient and regular. We are replaced diminished-1 modulo 2 n +1 adder by 2-stage n-bit adder. The remainder of the paper is organized as follows: mathematical formulation of Diminished-1 number representation computation of modulo multiplier is presented in Section II. The proposed structures are presented in Section III. Hardware and time complexity of the proposed structures are discussed and compared with the existing structures in Section IV. Conclusion is presented in Section V. II. DIMINISHED -1 NUMBER REPRESENTATION The modulo 2 n +1 arithmetic operations require (n+1) bit operands. To avoid (n+1)-bit circuits, the diminished-1 number system [15] has been adopted. Let d[A] be the diminished-1 representation of the normal binary number ] 2 , 0 [ n A  , namely 1 2 1 ] [    n A A d (i) In (i), when ] 1 2 , 0 [ ] [ , 0    n A d A ,is an n -bit number, therefore (n+1) -bit circuits can be avoided in this case. However, n n d A d A 2 1 ] 0 [ ] [ , 0 1 2       (ii) Is an (n+1) -bit number. This leads to special treatment for d [0]. The diminished-1 arithmetic operations [15] are defined as ] 1 2 , 0 [ ] [ , ] [ ] [     n A ifd A d A d (iii) Area and Power Efficient Modulo 2^n+1 Multiplier