Exploiting Parallelism in Double Path Adders’ Structure for Increased Throughput of Floating Point Addition Alexandru Amăricăi Mircea Vlăduţiu Lucian Prodan Mihai Udrescu Oana Boncalo Advanced Computing Systems and Architectures (ACSA) Research Group, Computer Science and Engineering Department, “Politehnica” University of Timisoara E-mail:{alexandru.amaricai, mvlad, lprodan, mudrescu, oana.boncalo}@cs.upt.ro Abstract This paper proposes a novel approach for increasing the performance of the floating point addition, by efficiently exploiting both paths from the classical double path adder. Thus, it becomes possible to execute two floating point additions simultaneously using a single adder, each on a different path. Performing two floating point additions in this manner will requires duplication of the signs and exponent computation modules. The cost estimates show a 20% increase of the active area for the proposed adder compared with other floating point adders. In terms of performance, the latency of the proposed adder is slightly higher with respect to other double path adders. However, the increased latency is compensated by the increased throughput obtained. Key words: Floating point addition, double path adders 1. Introduction Floating point addition/subtraction is the most common floating point operation, counting more than half from all floating point instructions [8]. Therefore, a lot of effort has been spent on improving the performance of this crucial operation. However, floating point addition (we use addition to mean add or subtract operation) is the most difficult basic floating point operations (addition, multiplication and division) due to the large number of sequentially dependent operations required. In order to reduce the number of sequential operations, the double path addition algorithm was developed [4]. This type of floating point adders are based on the splitting of the significand data path in two. The number of sequential operations performed on the double path adder is reduced to almost half, thus increasing the performance of the most common floating point operation. The selection of the path, however, varies in the many types of double path adders. The first selection criteria [4] used was the exponents’ difference: if the exponents’ difference is greater than 1 then one path is chosen (called the FAR path), while if the exponents difference is 1 or 0 than the other path is chosen (called the CLOSE path). In [1][5][7][10][11] adders, the selection criteria is: the CLOSE path is used for effective subtractions when the exponents difference is 1 or 0, while the FAR path is used for the other cases. Although there are many types of double path adders, they are all designed and optimized for only one single floating point addition at a time. This paper proposes a new type of floating adder that can perform two floating point addition simultaneously. The proposed adder is based on the fact that two consecutive, independent floating point additions can be performed each on a different path. The selection criteria used maximize the probability of executing two floating point operations at the same time. The CLOSE path is used both for effective addition or subtraction when the exponents’ difference is 1 or 0, while the FAR path is used for all effective additions and for effective subtractions when the exponents’ difference is greater than 1. Performing two floating point additions simultaneously requires duplication of the exponents and sign computation circuits, because two exponents and two signs must be computed. Another important change with respect to [1][4][5][7][8][10] adders is that a new circuit is placed before splitting of the significand data path. The new dedicated circuit plays the role of dispatching the operands on the proper path. Thus, an efficient exploitation of the parallelism of the double path adders is achieved. This paper is organized as follows: Section 2 is an overview of floating point addition, in Section 3 the proposed adder is detailed, while cost and performance estimates are presented in Section 4; last section presents the conclusions. 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) 0-7695-2978-X/07 $25.00 © 2007