3482 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 Behavioral Study of Single-Event Burnout in Power Devices for Natural Radiation Environment Applications M. Zerarka, P. Austin, G. Toulon, F. Morancho, H. Arbess, and J. Tasselli Abstract—Two-dimensional numerical simulations have been performed to define the sensitive volume and triggering criteria of single-event burnouts (SEBs) for standard and superjunction MOSFETs and planar and trench IGBTs for different config- urations of ionizing tracks and for different conditions of po- larization and temperature. The analysis of the results gives a better understanding of the SEB mechanism in each structure and a comparison of behavior and robustness of these technologies under heavy-ion irradiation. Index Terms—MOSFET, planar IGBT, safe operating area (SOA), sensitive volume, single-event burnout (SEB), superjunc- tion (SJ) MOSFET (SJ MOSFET), TCAD simulations, trench IGBT, triggering criteria. I. I NTRODUCTION H IGH-VOLTAGE devices are vulnerable to the effect of natural radiation environment (NRE). This environment is composed of particles of various nature and energy such as heavy ions which can cause the destruction of these devices. In order to protect them against NRE effects, many studies have been carried out to understand the failure modes. Single- event burnout (SEB) is one of the catastrophic effects which could cause power device failure in space systems. Heavy ions inducing destructive failures in power MOSFETs have been extensively studied and are related to the existence of the par- asitic bipolar junction transistor inherent to the device [1], [2]. In IGBTs, destructive electrical failures were already observed [3], and those induced by heavy ions were observed in 1992 and 1993 by Rockwell and Boeing companies [4]. The adopted trig- gering criterion was only a critical linear energy transfer (LET) before the influence of the ion penetration depth was investi- gated [5]–[7]. Experimental observation of SEB in high-voltage power devices—MOSFET and IGBT—was reported in [8], demonstrating that avalanche conditions are not needed to trig- ger the IGBT, a heavy ion being able to induce latch-up, con- trary to power MOSFETs. Single-event gate rupture (SEGR) Manuscript received August 4, 2012; revised September 25, 2012; accepted September 27, 2012. Date of current version November 16, 2012. This work was supported by the Fondation de Recherche pour l’Aéronautique et l’Espace (http://www.fnrae.org/) within the framework of EPOPE project. The review of this paper was arranged by Editor M. Darwish. The authors are with the Université de Toulouse, UPS, and LAAS, CNRS, 31077 Toulouse, France (e-mail: mzerarka@laas.fr; austin@laas.fr; gtoulon@laas.fr; Frederic.Morancho@laas.fr; houssam.arbess@laas.fr; josiane.tasselli@laas.fr). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2012.2222889 and SEB testing have been carried out by McDonald et al. [9] on three types of commercial 600–1200-V planar IGBTs. They found that they are all sensitive to SEB and SEGR, but mea- surements at a reduced V CE value, from 270 to 330 V, indicated a significant reduction in both measured SEB/SEGR sensitivity allowing to use them in space applications. Recently, a com- parative study between punch-through (PT) planar, PT trench, and field-stop (FS) trench IGBTs conducted by a Japanese team have shown that FS-IGBT exhibits the highest threshold voltage against SEB and has a particularly high destruction tolerance against cosmic rays [10]. Currently, the trend is to use rather long ranges, which corresponds to the track length penetrating the device, that are able to cross the epitaxial layer of the classic planar-type VDMOS. Liu, however, investigated the range effect on both SEB and SEGR phenomena [5] and recommends the use of light short-range ions, not to be confused with the appearance of SEGR during SEB tests. The test results carried out on 600-V prototypes show no significant effect of the range on the SEB safe operating area (SOA) (for ranges from 30 to 300 μm), together with Marec et al. [6] which suggest that the criterion is a critical deposited charge in the epitaxy, the latter defining also the sensitive volume. On the other hand, Luu et al. [7] show an influence of the ion range in commercial MOSFETs; they define the epitaxial layer as the sensitive volume. We also have al- ready reported the effect of the ion range on 600-V IGBTs [11]. Few works are related to superjunction (SJ) MOSFET (SJ MOSFET). Huang et al. showed that the presence of the horizontal electric field and the smaller vertical electric field in the SJ device reduces significantly its vulnerability to SEB and SEGR compared to the standard power MOSFET [12]. Ikeda et al. showed experimentally that there was no significant difference in SEB tolerance between the two MOSFET devices. However, SJ MOSFET could have better SEB tolerance by decreasing the die size while maintaining a low ON-resistance and applying the hardening technique for the standard power MOSFET structure [13]. In this context, we have performed a simulation work by 2-D TCAD, in order to define the SOA, the sensitive volume, and the criteria for SEB triggering induced by heavy ions, for various power devices (standard and SJ MOSFETs and planar and trench IGBTs). The first part of this paper presents the 2-D simulation results for the definition of the sensitive volume defined by the minimum LET triggering a SEB, according to the range and depth of ion generation. The analysis of these 0018-9383/$31.00 © 2012 IEEE