Performance Scalability of a Remote Sensing Application on High Performance Reconfigurable Platforms Esam El-Araby 1 , Mohamed Taher 1 , Tarek El-Ghazawi 1 , Aliaa Youssif 1 , Richard Irish 2 , and Jacqueline Le Moigne 2 1 The George Washington University, 2 NASA/Goddard Space Flight Center {esam, mtaher, tarek, aliaay}@gwu.edu, rirish@pop400.gsfc.nasa.gov, Jacqueline.LeMoigne@nasa.gov Abstract The trend for remote sensing satellite missions has always been towards smaller size, lower cost, more flexibility, and higher computational power. Reconfigurable Computers (RCs) combine the flexibility of traditional microprocessors with the power of Field Programmable Gate Arrays (FPGAs). Multi-node systems of High-Performance RCs (HPRCs) are becoming more popular recently as dictated by the requirements of many large-scale applications. Therefore, HPRCs are a promising candidate for on- board preprocessing. However, in order to meet the aggressive demands of those large-scale applications such as remote sensing, scalability of such applications on HPRCs may become an issue that can negatively affect the overall performance. In this paper, we investigate the potential of using HPRCs for on-board preprocessing by studying and characterizing the scalability of the Landsat 7 ETM+ ACCA algorithm on two of the state- of-the-art reconfigurable platforms, SRC-6 and Cray- XD1. 1. Introduction Remote sensing satellite missions have always been characterized by the demand of smaller size, lower cost, and more flexibility. On-board processing, as a solution, permits a good utilization of expensive resources. Data processing can be performed on-orbit prior to downlink resulting in the reduction of communication bandwidth as well as in simpler and faster subsequent computations to be performed on ground stations. Consequently, on-board processing can reduce the cost and the complexity of the On-The- Ground/Earth processing systems. Furthermore, it enables autonomous decisions to be taken onboard which can potentially reduce the delay between image capture, analysis and action. This leads to faster critical decisions which are crucial for future reconfigurable web sensors missions as well as planetary exploration missions. Reconfigurable Computers (RCs) combine the flexibility of traditional microprocessors with the power of Field Programmable Gate Arrays (FPGAs). These platforms have always been reported to outperform the conventional platforms in terms of throughput and processing power within the domain of cryptography [1], image processing [2], and remote sensing applications [2], [3]. Multi-node systems of High- Performance RCs (HPRCs) are becoming more popular recently as dictated by the requirements of many large- scale applications. These systems are characterized by lower form/wrap factors compared to parallel platforms, and higher flexibility than ASIC solutions. Therefore, HPRCs are a promising candidate for on- board preprocessing. The SRC-6 Reconfigurable Computer and Cray-XD1 are examples of this category of computers [4], [5], [6] and are used here for this purpose. However, in order to meet the aggressive demands of those large-scale applications such as remote sensing, scalability of such applications on HPRCs may become an issue that can negatively affect the overall performance. In this paper, we investigate the potential of using HPRCs for on-board preprocessing by studying and characterizing the scalability of the Landsat 7 ETM+ ACCA algorithm [7] on two of the state-of-the- art reconfigurable platforms, SRC-6 and Cray-XD1. 2. Systems and Application In this work, two main systems have been used. These are the SRC-6 and the Cray-XD1 at The George Washington University, High-Performance Computing Laboratory (HPCL). Landsat 7 ETM+ ACCA algorithm was selected to determine an almost practical bounds on the potential performance of HPRCs should all architectural challenges be alleviated and to gain an insight into the system level programmability and performance issues apart from those known for general high-performance computers. 2.1. SRC-6 Reconfigurable Computer SRC-6 platform consists of one or more general- purpose microprocessor subsystems and one or more MAP ® reconfigurable processor subsystems [4]. These subsystems are interconnected through a Hi-Bar Switch