Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology David Bol * , Julien De Vos, Renaud Ambroise, Denis Flandre, Jean-Didier Legat Microelectronics Laboratory, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium article info Article history: Received 15 March 2008 Received in revised form 25 April 2008 Accepted 6 June 2008 Available online 8 November 2008 The review of this paper was arranged by Dimitri Lederer and Jean-Pierre Colinge PACS: 85.40 84.30 Keywords: Ultra-low-power Leakage reduction High temperature SOI abstract For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high temperature, the power consumption of such circuits is completely dominated by static power dissipation due to leakage currents. In this contribution, we propose a new logic style, namely ultra-low-power (ULP) logic style which achieves negative V gs self-biasing, to benefit from the small area and low dynamic power of high-performance deep-submicron SOI technologies while keeping ultra-low leakage, even at high temperature. In 0.13 lm partially-depleted SOI CMOS tech- nology, the static power consumption at 200 °C is reduced by nearly three orders of magnitude at the expense of increased delay and area. Ó 2008 Elsevier Ltd. All rights reserved. 1. Introduction Ultra-low power applications are an emerging field of the inte- grated circuit (IC) market. RFID tags, biomedical devices and sensor networks typically feature low computational load but require minute power consumption at low cost, in order to operate for a long time on small batteries or harvest power either from the envi- ronment or a wireless data link. Power consumption of such appli- cations greatly benefit from a clock frequency reduction, which is affordable thanks to the low computational load [1]. The supply voltage V dd can also be lowered as it reduces quadratically the dy- namic power consumption. When entering the deep-submicron and nanometer eras, dynamic power consumption of ultra-low- power IC’s is further reduced thanks to lowered switched capaci- tances [2]. However, technology scaling also leads to an ever increasing static power dissipation due to leakage currents [3]. Leakage mitigation techniques are thus required because other- wise, static power increase would ruins the benefit brought by dy- namic power reduction. Classical leakage mitigation techniques rely on the use of technologies with multiple threshold voltages (V t ) or reverse body biasing [3]. In the industrial sector, ultra-low-power circuits are also used for distributed process monitoring and control. In comparison to biomedical devices, industrial applications have very different environment conditions. In applications such as oil drilling, down- hole monitoring, combustion engine or harsh-environment indus- trial process control, the operating temperature can be very high, up to 300 °C. At high temperature, the behavior of MOSFETs is de- graded and leads to robustness issues at low voltage and orders-of- magnitude higher leakage currents [4,5], which can hardly be dealt with by traditional leakage mitigation techniques, especially in deep-submicron technologies. In this article, we propose a new leakage mitigation technique based on the ultra-low-power (ULP) transistor concept [6] to ben- efit from the low die area and low dynamic power of high-perfor- mance CMOS technologies with very deep-submicron channel lengths while keeping ultra-low leakage, even at high temperature. The proposed ULP transistor achieves negative V gs self-biasing and allows to build an ULP logic style with orders-of-magnitude reduc- tion of leakage current at the expense of increased delay. We show that ULP logic style is a robust and straightforward technique to build ultra-low-power high-temperature digital circuits in stan- dard high-performance SOI technology. 0038-1101/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2008.06.045 * Corresponding author. Tel.: +32 10 47 8134; fax: +32 10 47 2598. E-mail addresses: david.bol@uclouvain.be (D. Bol), Renaud.ambroise@uclou- vain.be (R. Ambroise), denis.flandre@uclouvain.be (D. Flandre), jean-didier.lega- t@uclouvain.be (J.-D. Legat). Solid-State Electronics 52 (2008) 1939–1945 Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse