Resource efficient implementation of a 10Gb/s radio receiver baseband in FPGA Christer Svensson Linköping University 58183 Linköping, Sweden +46 705281223 chs@isy.liu.se Lei Bao Ericsson Research Ericsson AB Göteborg, Sweden lei.bao@ericsson.com Zhongxia He Chalmers University of Technology Göteborg, Sweden Zhongxia@chalmers.se Herbert Zirath Chalmers University of Technology Göteborg, Sweden Herbert.Zirath@chalmers.se Jingjing Chen Ericsson Research Ericsson AB Göteborg, Sweden jingjing.chen@ericsson.com ABSTRACT Data-rate of wireless links are increasing fast, particularly when new carrier bands with very high bandwidth becomes available. Utilizing the full bandwidth for a single carrier facilitates very large baud-rates. When the baud-rates approaches or exceeds Gbaud, the implementation of the digital baseband is no longer a simple extension of existing methods. In the present paper we propose a resource efficient implementation of digital baseband for multi-Gbaud rates in a standard FPGA utilizing Xilinx Simulink-based System generator design and verification tool. Categories and Subject Descriptors B.7.1 [Integrated circuits]: Types and Design Styles – Algorithms implemented in hardware, Gate arrays. General Terms Design. Keywords FPGA design, Radio communication baseband. 1. INTRODUCTION Point-to-point microwave is today the dominant technology for mobile backhaul. Driven by the growth of video traffic, mobile data traffic is estimated to increase 10-fold by 2016 [1]. Microwave backhaul is consequently regarded as a potential bottleneck, given that microwave channels traditionally utilize narrow bandwidth. However, millimeter-wave band channels are sufficiently wide to support ultra-high data rate wireless transmission [2]. The recently allocated 70/80GHz band, for example, offers multi-gigabit opportunity for multi-km reach, as a cost-efficient and flexible alternative to fiber for future backhaul. Taking the advantage of wide available bandwidth, Gbps capacity can be reached using simple modulation formats with spectral efficiency ≤ 1bit/s/Hz [3-5]. Improving the spectral efficiency is a key approach for a higher capacity in a limited frequency band. 6Gbps over 80GHz based on four channel frequency multiplexing was demonstrated with 2.4bit/s/Hz [6] and 10Gbps over E-band based on eight channel frequency multiplexing was demonstrated with 3.2bit/s/Hz [7]. Driven by the widely used Ethernet standards, there is a demand for wireless technologies to support even 10GbE, as competition to the wired counterparts [2]. And it has been demonstrated that this can be achieved in the 70/80GHz band [7], [8]. So, millimeter-wave bands make high band-width and therefore high baud-rates available. However, when baud-rates approach or exceed 1Gbaud, the implementation of the baseband is no longer a simple extension of existing methods. Instead, the baseband problem needs to be reconsidered, and simple mapping of algorithms to standard hardware needs to be replaced by a hardware-aware approach. In this approach both the choice of algorithms and the implementation of these are steered by hardware awareness. In this work, we present a resource-efficient implementation of a multi-gigabit radio baseband in a standard FPGA. The proposed solution is aimed for a 10Gb/s backhaul line-of-sight link, utilizing a baudrate of 2.5Gbaud in conjunction with 16QAM modulation, and adapted to the 70/80 GHz band [8]. The line-of- sight target simplifies the baseband requirements, as we do not expect a need for an equalizer. The tasks to be implemented in the baseband are therefore limited to symbol timing recovery (STR), Carrier recovery (CR) and Symbol recovery (slicing). Forward error correction (FEC) and other symbol-level tasks are not treated in this work. 2. BASIC CONSIDERATIONS In fig.1 we show an overview of the receiver [8]. The carrier frequency is 70 or 80GHz, and is downconverted to an IF of 6GHz. The IF is further downconverted to zero frequency (baseband), followed by a baseband filter and some gain. The filtered baseband signal is finally fed into an ADC (2.5GS/s, 12b), which sampling frequency is controlled by a sampling oscillator, SO. The SO is controlled by a signal from the Digital baseband, see below. Finally the ADC output is fed to the Digital baseband. In the search for an efficient implementation of a 2.5Gbaud wireless receiver, we must recognize that 2.5GHz is a very high frequency. This strongly affects our choice of sampling rate and ADC, as few ADCs are available at sampling rates above 2.5GS/s. We must therefore limit the oversampling ratio to a minimum; we have chosen an oversampling ratio of 1. Next, we need to choose clock frequency for the digital system. Most modern FPGAs have an upper clock frequency of about 500MHz for DSP blocks, and it is difficult to be too close to this limit. We have therefore chosen a clock frequency of 312.5MHz (2.5GHz/8). This leads to the need for 8x parallelism in the main datapath. The high clock