ECC Design for Fault-Tolerant Crossbar Memories: A Case Study Nor Zaidi Haron1,2 Said Hamdioui1 Zaiyan Ahyadil 1 Computer Engineering Laboratory, Delſt University of Technology, T he Netherlands 2 Faculty of Electronics and Computer Engineering, Univeristi Teknikal Malaysia Melaka, Malaysia {N.Z.B.Haron, S.Hamdioui}@tudelſt.nl, zaidi@utem.edu.my Abstract-Crossbar memories are promlsmg memory tech- nologies for future data storage. Although the memories offer trillion-capacity of data storage at low cost, they are expected to suffer from high defect densities and fault rates impacting their reliability. Error correction codes (ECCs), e.g., Redundant Residue Number System (RRNS) and Reed Solomon (RS) have been proposed to improve the reliability of memory systems. Yet, the implementation of the ECCs was usually done at software level, which incurs high cost. This paper analyzes ECC design for fault-tolerant crossbar memories. Both RS and RRNS codes are implemented and experimentally compared in terms of their area overhead, speed and error correction capability. The results show that the encoder and decoder of RS requires 7.5x smaller area overhead and operates 8.4x faster as compared to RRNS. Both ECCs has fairly similar error correction capability. I. INTRODUCT ION The quest for new memory technology that can provide rther scalability, yet able to tolerate reliability failures has made fault tolerance as one of the key requirements [1]-[6]. Crossbar memory is one of the emerging new memory tech- nologies able to offers trillion-capacity of data storage at low power consumption and reduced fabrication cost. However, these advantages do not come for ee as several challenges need to be resolved [3]. One of the challenges is that the memories are likely to suffer om high defect densities and fault rates impacting their reliability. In order to improve the reliability of crossbar mem- ories, error correction codes (ECCs) such as Hamming, Low-Density Parity-Check (LDPC) and Bose-Hocquengham- Chaudhuri (BCH) codes [7]-[11] have been proposed. Accord- ing to [5], [6], defects and faults in crossbar memories tend to induce cluster errors; hence, ECCs able to correct such errors, such as RS [12] and RRNS [13]-[15], are required. adi- tionally, these ECCs have been implemented using soſtware resulting in low performce; this make such implementation unsuitable for scalable yet unreliable crossbar memories. This paper studies ECC design for fault-tolerant crossbar memories. The encoder and decoder of both RS and RRNS are designed and implemented. An evaluation in tes of their area overhead and decoding speed as well as error correction capability is carried out. The evaluation shows that the encoder and decoder of RS requires smaller area and operates faster as compared to that of RRNS. Moreover, both ECCs can coect almost equivalent numbers of errors. The rest of the paper is organized as follows. Section II gives 978-1-61284-292-9/10/$26.00 ©2010 IEEE 61 the background of crossbar memories and error correction codes. Section III presents the theory of RS and RRNS that are used in our work. Section IV explains the design of the encoder and decoder for both ECCs. Section V analyzes and compares the area overhead, speed and error correction capability of the considered ECCs. Section VI concludes this paper. II. BACKGROUND This section gives the background required to rther under- stand the paper. It starts with explaining crossbar memories, thereaſter error correction codes. A. Crossbar Memories Figure l(a) shows one of the crossbar memories referred to as CMOS/Molecular (CMOL) memory [7], [8]. CMOL memory provides the utmost data storage capacity as huge as lTbitlcm 2 , which is about three magnitude denser than the existing semiconductor memories. In addition to the data storage, the novelties of this hybrid memory are: (i) the memory array is stacked above the peripheral circuits (3D stacking IC instead of planar Ie), and (ii) the memory array are formed by non-CMOS devices instead of CMOS and/or capacitor. The memory array consists of nanowire crossbars with reconfigurable two-terminal nanodevices embedded at each crosspoint. Because non-CMOS-based devices are incapable to perform the periphery tasks (e.g., sensing, amplification, etc.), nanoscale CMOS is required to structure the peripheral circuits [7], [8]. Two sets of CMOS-to-nano (CtN) interface pins connect the memory array to the peripheral circuits; see Fig. 1(b). These CtN interface pins are different in height such that the short pins connect the lower nanowires, while the tall pins connect the upper nanowires. In order to write to and read om the memory, a sufficient voltage is biased across the targeted two-teinal nanodevices (memory cells) om the CMOS-based peripheral circuits through the CtN interface pins to the corresponding nanowires [7], [8]. For writing, the voltage must be larger than the threshold voltage of the two-terminal devices to  them on (represent 1) and smaller to  them off (represents 0). For reading, a smaller voltage is used. Note that the value of the voltages depends on the two-teinal nanodevices used as the memory cells [7].