A Fully-Integrated Digital-Intensive Polar Doherty Transmitter Yiyu Shen # , Mohammadreza Mehrpoo # , Mohsen Hashemi # , Michael Polushkin # , Lei Zhou #* , Mustafa Acar * , Rene van Leuken # , Morteza S. Alavi # , Leo de Vreede # , # ELCA group, Delft University of Technology, Delft,The Netherlands * Ampleon, Nijmegen, The Netherlands Abstract — This paper presents an advanced 2.3–2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40 nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is +21.4dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz 64-QAM signal, the measured EVM is better than -30 dB while the average drain efficiency is 24%. Index Terms — Doherty transmitter, digital-intensive polar, efficiency enhancement, DPD, phase modulator, on-chip combiner. I. I NTRODUCTION Recently, digital-intensive transmitters (DTX) [1], [2], [3] are gaining attention due to their excellent hardware scalability with nanoscale CMOS and their great potential to incorporate extensive digital correction circuitries such as digital pre-distortion (DPD). These properties are essential in achieving high system integration, linearity, and efficiency at low cost. However, due to the large peak-to-average power ratio (PAPR) of a modern complex modulated baseband signal, which typically yields to the severe degradation of the average efficiency, various efficiency enhancement techniques, like Doherty [4], [5], outphasing [6], and supply modulation [7], are currently also adopted in DTXs approaches. Among them, the Doherty topology is popular due to its large video and RF bandwidth along with its relative low hardware complexity. However, the design of a fully-integrated digital Doherty PA exposes several challenges. First, PA topologies that feature linear operation, typically do not benefit from switching operation [6]. Second, on-chip matching networks, especially in the main path of the Doherty PA, are lossy, leading to a significant efficiency drop in their power back off (PBO) region [4]. To address these issues while achieving high overall system efficiency, spectral purity, and video bandwidth, a digital-intensive polar Doherty transmitter is proposed and realized in 40 nm bulk CMOS. To the authors knowledge, Decoder AM_M MAIN BRANCH Limiter PM_MI PM_MQ 4 DPA Phase Modulator Implementd Chip in 40nm CMOS SPI 4 4 Decoder AM_P PM_PI PM_PQ 4 DPA 4 4 Divide by 4 CK0° CK90° CK180° CK0° CK90° CK90° CK180° Phase Modulator PEAK BRANCH Impedance Inverter 4xf0 50Ω Digital Baseband Limiter Input Balun L i m i t e r P L i m i t e r Fig. 1. Block diagram of the proposed digital-intensive TX. this architecture is the first bits-in RF-out single-chip DTX employing the Doherty topology. II. SYSTEM ARCHITECTURE OF PROPOSED TX The block diagram of the proposed DTX is depicted in Fig. 1. The DTX consists of digital baseband processing unit, clock divider, interpolation filter, wideband phase modulators and digital PA branches. The 4×f 0 single-ended off-chip clock, where f 0 is the carrier frequency, is applied to an on-chip balun to convert the single-ended clock to a differential signal. This differential clock is then applied to a divide-by-4 circuit to generate the desired multi-phase clock signals at f 0 . These clock signals are then fed to the main and peak phase modulators of the Doherty branches with the clock signals of the peak branch lagging 90 degree those of the main branch, emulating the input λ/4 transmission line in a conventional Doherty topology. Employing an on-chip CORDIC, the digital in-phase (I ) and quadrature (Q) baseband signals are converted into their envelope (AM) and phase (PM) polar representation. The baseband AM signal is first interpolated and after splitting into AM main and AM peak , they are fed to the main and peak digital PAs (DPA). Note that preceding the PA stages, the envelope signals are first converted from a binary bit-stream into thermometer code and then are applied to the (digital) up-converted mixers. Meanwhile, 978-1-5090-4626-3/17/$31.00 © 2017 IEEE 2017 IEEE Radio Frequency Integrated Circuits Symposium RMO3B-3 196