Indian Journal of Science and Technology Vol. 3 No. 4 (Apr. 2010) ISSN: 0974- 6846 Research article “Cryptography” Sokouti et al. ©Indian Society for Education and Environment (iSee) http://www.indjst.org Indian J.Sci.Technol. 459 FPGA implementation of improved version of the Vigenere cipher Massoud Sokouti 1 , Babak Sokouti 2 , Saeid Pashazadeh 1 and Leili Mohammad Khanli 3 1 Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran; 2 Faculty of Engineering, Islamic Azad University-Tabriz Branch, Tabriz, Iran; 3 Faculty of Mathematical Sciences, University of Tabriz, Tabriz, Iran. m_sokouti@yahoo.com Abstract The use of cryptography has become increasingly important in recent years. Currently there are several good methods for encryption like AES and DES. Both of these algorithms require several rounds to encrypt a relatively small block of data. Stream ciphers, like Vigenere and Caesar in particular, only require one round. The Vigenere and Caesar ciphers, however, can be easily broken. Improved version of the Vigenere algorithm is obtained by adding random bits of padding to each byte to diffuse the language characteristics and this make the cipher unbreakable. In this paper we will present an efficient method for hardware implementation of the improved Vigenere algorithm. Keywords: Cryptography; Vigenere algorithm; FPGA. Introduction The use of cryptography in modern day communication systems is becoming increasingly important as more and more people making use of electronic transactions (Dreyere, 2004). As we know AES and DES are good ways for encryption but the only big problem of these two ciphers is that the key needs several rounds to encrypt a small block of data. For a long period of time, the data encryption standard (DES) was considered as a standard for the symmetric key encryption. This standard has a key length of 56 bits. For the time being, this key length is considered small and can easily be broken. For this reason, the National Institute of Standards and Technology (NIST) announces, after a competition between 15 algorithms, that the Rijndael cipher will replace the DES cipher and will become a new advanced encryption standard (AES). The Rijndael cipher has three possible block and key lengths: 128, 192 or 256 bits. Therefore, the problem of breaking the key becomes more difficult (Stallings, 2003). The advanced encryption standard (AES) is based on arithmetic block cipher in finite Galois field, GF (2 8 ), and is a symmetric block cipher that encrypts 128-bit plaintext data with a 128 bit, 192 bit, or 256 bit cipher key (NIST, 2001). As we know AES requires 11 rounds. Since Nov 2001, various AES implementations using ASICs or FPGAs have been reported some of them are focusing on small chips and some are focusing on high throughput IVV is a good choice for encryption because it uses the Vigenere cipher and it needs only one round (Sokouti & Sokouti, 2009). In this paper we will implement the IVV (Sokouti & Sokouti, 2009) by FPGA. This simulation is done in Quartus II 6 and the devices which are used are Startix. Vigenere This cipher is one of the best known of manual polyalphabetic ciphers and is named after Blaise de Vigenere. Just like the other classic ciphers we have a message that we want to encrypt which is named plaintext and another stream for encrypting which is named key. After encrypting plaintext and the key a message is produced that is named cipher text. In this cipher we should repeat key characters in order to make the length of the key as same as the length of the plain text. In other words, having keywords length m, an alphabetic character can be mapped to one of m possible alphabetic characters (assuming that the keyword contains m distinct characters). Such a cryptogram is called polyalphabetic cryptosystems. If the message is an English text containing n characters with all punctuation and spaces removed, and if we use the correspondence a = 0, b = 1… z = 25, for plaintext p 1 , p 2 … p n and key k 1 , k 2 … k n , the i th character of the cipher text is given by this method (Piper & Murphy, 2002; Bishop, 2003; Stallings, 2003): Fig.1. Sample Vigenere encryption. Cipher text is our output after encryption, and clk is our clock, and key is the key of the Vigenere cipher, and plain_text is the text which should be encrypted, s is starting simulation. C i = (p i + k i ) mod 26 We can see a sample simulation Table 1. Diffusion of random bits, r is a random bit; m is the bit value of the message. F(x) Byte 1 Byte 2 0 rmmmmmmm mrrrrrrr 1 rmmmmrmm mmrrrrrr 2 mrmmmrmm mrmrrrrr 3 rmmrmmrm mrmmrrrr 4 mmrmrmrm rmrmmrrr 5 rmmrmrmr mrmrmmrr 6 mrmrmrmr mrmrmrmr 7 rmrmrmrm rmrmrmrm