FLASH Modelling/or Wearleveling Algorithms Syed Aamer Hussain Department of Electrical Engineering National University of Sciences and Technology Islamabad, Pakistan aamer.hussain@seecs.edu.pk Abstract: The recent trend in the stora g e industr is the use of fash based solid state disk (SSD) as compared to the power hun g r mechanical disk. The endurance of Flash based SSD is still (important area of research) a major challen g e. However improvement can be made by considerin g the desi g n of FTL (ash translation layer) and time it takes to access or erase the data. Improvements can be made in all the major functions of FTL. which includes implementation of wear levelin g and address translation. Developin g fast and reliable al g orithms for wear levelin g will not only increase the lie time of the fash devices but will also ensure faster erase and write operations. This paper presents a test development environment for modelin g the fash stora g e which is used for the wear levelin g al g orithm testin g usin g Matlab. Cost A g e Times (CAT) al g orithm is analyzed usin g the test-bed environment and enhancement is proposed which has improved erasure count by 25%. Keywords- Solid State Drive; Flash drives; FTL; testbed; Wear levelin g ; Cost A g e Tmes 1. INTRODUCTION Flash solid state devices are capturing much of the storage industry and are expected to replace much of the traditional storage class by the end of this decade. The strong points of this technology are its less power consumption, higher data read/write rates, higher installation performance and robustness fom shock then the mostly used magnetic disks. These advancements have made them the ideal candidate for enterprise and server side storage technology [1] [2]. Flash devices are made up of foating gates. These devices are divided into blocks containing many pages. Page is the smallest entity that can be written and accessed for read. Each page contains specifc number of bytes which are all written at once [3]. Data is stored as electrical impulses in the network of foating gates. Block is the largest entity of a FLASH device but the smallest which can be erased. Two design approaches that are being followed in high density fash memory development uses NAND and NOR structures. The two types are distinctive in terms of density, performance, and operating characteristics. NAND fash devices have higher density as compared to NOR but in case of performance both types are comparable. In term of erase latency, NAND fash devices have low erase latency of the order of milliseconds, whereas NOR fash device have an This work is sponsored by NUST 978-1-4577-1169-5/11/$26.00 ©2011 IEEE Abdullah Mansoor Department of Electrical Engineering National University of Sciences and Technology Islamabad, Pakistan abdullah.mansoor@seecs.edu.pk erase cycle of hundreds of milliseconds. Considering read/write cycles NOR FLASH have about 4-5 times higher read speed with a similar 4-5 time lower write speed with the ability of random access. NAND also has lower erase latency then the counterpart [4]. Considering the physical structure NOR fash devices have a simple device structure since they provides access to individual cells but at a cost of increase in the cell area since each drain and source requires individual connection with the bit and source line. For this reason they are used in a system that needs byte-addressable operations with fast read speed like booting fom fash or to execute code fom fash. NAND fash memory devices on the other hand have a compact structure in which a single contact lies with the bit line allowing it to scale to higher densities. But this single contact structure causes slow cell access since a single cell cannot be accessed; the device has to access it through other cells and because of it NAND fash can be read or programmed only in the unit of a page (512 bytes or 2 Kbytes) [21] [22]. Bit Line Bit Line Word Line Word Line ,- Cell -- : = ell Word Line Word Line Word Line Word Line Source Line Source Line Figure I NAND and NOR Flash Architectures Both the NAND and NOR fash devices are frther sub categorized into Single layer cell (SLC) which can store single bit per cell and multiple layer cell (MLC) which can store more than a single bit per cell [5]. SLC devices are much more reliable since the life time of such devices is much longer than their counterart, but still their cost reduces their competition with the MLC devices. MLC devices on the other hand have limited number of erase cycles available for their blocks. On 267