A New Clustering Based Routing Algorithm for NoC Abdelmalek Bouguettaya, Mohamed Taher Kimour, and Salah Toumi Abstract-- With the increasing number of the integrated cores on a single chip, research into Network on Chip (NoC) becomes important. NoC has been proposed as a solution to replace the classic interconnections of Systems on Chip (SoCs) design. Topology and routing algorithm are important keys of the NoC design. In this paper, we propose a new fault-tolerant routing algorithm for Networks on Chip (NoCs). The proposed algorithm is based on a combination between a dynamic routing algorithm and a communication load clustering technique in a 2D mesh topology. Keywords – Networks on chip, Dynamic routing algorithm, Fault tolerance, Clustering, Mesh topology. I. INTRODUCTION Y the end of the decade, according to the International Technology Roadmap for Semiconductors [1], SoCs will grow to 4 billion transistors running at 10 GHz and operating below one volt [2].Typically, in these systems, a several complex heterogeneous components can be integrated such as programmable processors, memories, input–output interfaces, custom hardware, peripherals, external interface IP (intellectual property) blocks that need to communicate with each other and an on-chip communication architecture that serves as the interconnection fabric for communication between these components. These elements serve to increase performance and to reduce cost and improve energy efficiency [2, 3]. Several architectures based on a bus communication have been proposed since 1990 to handle the communication needs of emerging SoC designs [4].While integration increases the bus structure reach its limits in term of performance and it does not meet the needs of the new technology. Bus starts to be narrow and in the worst case it begins to block traffic. It will be less used in 5 or 10 years. The NoC is a new paradigm for System on Chip design [5]. This technology is come to replace the classic buses interconnection to interconnect the IP modules in SoCs. Nowadays, Networks on Chip are considered as a scalable solution for on chip communication. In the recent years, Network on Chip has emerged as a growing and important research field. Abdelmalek Bouguettaya, Salah Toumi, LERICA Laboratory, Department of electronic, email: amalek.bouguetaya@univ-annaba.org, salah.toumi@univ-annaba.org Mohamed Taher Kimour LASE Laboratory, Department of computer science University of Badji Mokhtar-Annaba Po. Box 12, Annaba, Algeria, email: 2kimour@yahoo.com. The most important aspects that distinguish the various NoC architectures are topology and routing algorithm. After determining the network topology, the routing algorithm is the responsible of deciding the path a message or a packet will take through the network to reach its destination. Our approach is based on a combination between a clustering technique and a dynamic routing algorithm in a 2D mesh topology. We show that such the proposed approach enhances the performance of the routing algorithm and provide better fault-tolerance value. The next section describes the Network on Chip technology (NoC) and its characteristics. In section 3, we present our approach. And finally, we conclude this paper and present the future works. II. NETWORK ON CHIP ARCHITECTURE The Network on Chip is a new paradigm comes to replace the classic interconnections (Tab.1) as point to point, crossbar, bus, etc…2D mesh NoC architecture is the most used topology due to its regularity, simplicity for routing and easy integration in FPGA circuit.All the links have the same length, thus exhibiting the same latency. TABLE I THE ADVANTAGES PROVIDED BY NOCS. problematic Solution provided by the on-chip networks Propagation delays Minimal impact because the global interconnections are divided into shorter paths with the possibility of pipelining. Clock distribution Modular architecture and packets transport mode: adapted as well as the synchronous approaches than multi- synchronous or asynchronous approaches. Bandwidth Generally high as several transport paths can be used in parallel. Scalability/Flexibility Regular architectures easily expandable depending on the number of IP without major degradation of temporal and electrical performances. Network on Chip is composed of three main building blocks (Fig.1). The first one is the link that allows connecting the nodes and transferring data between them and plays an important role in the performance of NoC architecture. The second block is the router; its main role is to route data from a B International Conference on Machine Learning, Electrical and Mechanical Engineering (ICMLEME'2014) Jan. 8-9, 2014 Dubai (UAE) http://dx.doi.org/10.15242/IIE.E0114006 9