LOW-POWER SYSTEMS-ON-CHIP Bus encoding architecture for low-power implementation of an AMBA-based SoC platform S. Osborne, A.T. Erdogan, T. Arslan and D. Robinson Abstract: Advanced microcontroller bus architecture (AMBA) is rapidly becoming the de facto standard for new system-on-chip (SoC) designs. The bus protocol is complex, making any peripherals that can interface to it valuable intellectual property (IP). This paper presents a low- power bus encoding architecture which is able to deal with the complex advanced high- performance bus (AHB) protocol within AMBA, which involves multiple burst transfers. The architecture is targeted for a low-power SoC platform to be used in a miniaturised low power application area. The paper describes the SoC platform and the bus encoding architecture, and provides results with a design synthesised at 0.35 mm CMOS technology indicating up to 22% power saving. 1 Introduction For CMOS circuits, most dynamic power dissipated is for charging and discharging node capacitances. Dynamic power dissipated by a CMOS circuit is of the form [1]: P chip / P N i¼1 C load i * V 2 dd * f * pt i ð1Þ The summation is carried out over all N nodes in the circuit, C load i is the load capacitance at load i, V dd is the power supply voltage, f is the frequency and pt i is the activity factor at node i. In a CMOS VLSI circuit that uses well designed gates, the switching activity accounts for over 90% of the total power consumption. In circuits optimised for low power, the total power dissipation at the I=O is typically around half of the total for the circuit. This is due to the significantly larger dimensions of the devices in the I=O pads required to drive the external capacitances and also the external capacitance from the I=O pins, wires and peripheral circuits. To produce a clearer model of the impact of I=O transitions, (1) can be simplified by assum- ing all nodes to have the same average load capacitance, and V dd and f to be the same for all nodes [1]: P chip / C average * V 2 dd * f * N (transitions) ð2Þ In fact, this is oversimplifying the situation as a huge variation exists between average node capacitance for on chip and I=O nodes. The capacitance associated with an external pin is typically larger than that of an internal node by 2–3 orders of magnitude. The model must, therefore, be further shaped to take account of this, as shown in the following [1]: P chip / C int * N (transitions) int þ C ext * N (transitions) I=O ð3Þ A clear model now exists for the total power dissipated by the chip being contributed by the internal and I=O factors. The number of internal transitions is generally much larger due to the greater number of nodes, but the load capaci- tance will be several orders of magnitude smaller. From this theory, the idea of coding can therefore be justified to decrease the number of transitions on the large capacitance side, even at the expense of slightly increasing the number of transitions in the internal circuit. Intuitively, the total power dissipation should decrease by decreasing the number of transitions on the high-capacitance side, as the number of internal transitions is already large and increasing it slightly is unlikely to be significant. 2 Bus coding techniques In general, bus encoding techniques aim to reduce the power consumption on a bus by mapping the information conveyed on the bus to a form which has less transition activity than the original. These are largely based on the fact that the relationships between the data can be devel- oped and exploited, between subsequent transmissions, to reduce the switching activity on the lines. This work focuses on off chip buslines, due to their high capacitive load which makes them a major contributing factor to the overall power consumption of the SoC device. Various low-power coding methods have been proposed in the literature for both address and data bus. For the address bus, coding techniques such as Gray [2], zero-transition activity (T0) [3], T0-XOR [4], offset [4] and pyramid code [5] have been used effectively. For data bus encoding, on the other hand techniques such as bus-invert [1, 6], transition signalling [6], BITS [7], codebook-based encoding [8] and probability-based mapping [9] have been investigated. In specific applications, when the characteristics of the used data can be exploited, techniques such as the Beach solution # IEE, 2002 IEE Proceedings online no. 20020448 DOI: 10.1049=ip-cdt:20020448 Paper first received 1st November 2001 and in revised form 3rd April 2002 S. Osborne and D. Robinson are with the Institute for System Level Integration, The ALBA Campus, Livingston, EH54 7EG, Scotland, United Kingdom A.T. Erdogan is with the Department of Electronics & Electrical Engineering, University of Edinburgh, Edinburgh EH9 3JL, Scotland, United Kingdom T. Arslan is with the Institute for System Level Integration and the University of Edinburgh 152 IEE Proc.-Comput. Digit. Tech., Vol. 149, No. 4, July 2002