Thin Solid Films 415 (2002) 32–45 0040-6090/02/$ - see front matter  2002 Elsevier Science B.V. All rights reserved. PII:S0040-6090 Ž 02 . 00502-3 Modeling 3D effects of substrate topography on step coverage and film morphology of thin metal films T. Smy *, S.K. Dew , R.V. Joshi a, b c Department of Electronics, Carleton University, Ottawa, Ont., Canada K1S 5B6 a Electrical and Computer Engineering, University of Alberta, Edmonton, Alta., Canada T6G 2G7 b IBM, T.J. Watson Research Center, Yorktown Heights, NY 10598, USA c Received 11 May 2001; received in revised form 19 January 2002; accepted 16 May 2002 Abstract This paper presents the use of three-dimensional (3D)-films to investigate 3D effects of microstructure and topography on the deposition of metal films over integrated circuit topography. 3D-films is a fully 3D thin film growth simulator which models both the evolution of the surface profile and the internal microstructure of the film. The simulator produces a detailed depiction of the film, including grain and columnar structure, and is capable of producing density and porosity information. This paper first presents the application of this simulator to specific problems posed by the sputter deposition of refractory metals as barriers and the filling of contacts and vias by electroplating of copper and CVD of tungsten. Specific problems addressed are step coverage over a variety of dual damascene topographies, the formation of notches and poor step coverage using directed sputtering and conformal filling of features. The program is used to address the ramifications of using geometric optimization of the viaycontact geometry and the application of resputtering fluxes. Finally, issues concerning incomplete filling of dual damascene structures using CVD and plating are addressed.  2002 Elsevier Science B.V. All rights reserved. Keywords: Sputtering; Structural properties 1. Introduction The creation of VLSI metallization structures is an increasingly difficult task. The requirements for deep sub-micron features, high reliability and low RC delay is a difficult combination to fulfill. The fabrication of vias ycontacts and lines in both oxide and ‘low k’ dielectrics involves the sequential deposition of refrac- tory metal liners and a conductive metal fill (usually Al or Cu). The refractory barriers need to be very thin to reduce overall line resistivity, but must be an adequate diffusion barrier to either the Cu or the Al. The fill step is required to be void free and of low resistivity. The dominant patterning technique for ‘state of the art’ VLSI backend processes is dual damascene. This procedure basically etches the line and via pattern into *Corresponding author. Tel.: q1-613-520-3967; fax: q1-613-520- 5708. E-mail address: tjs@doe.carleton.ca (T. Smy). the interlayer dielectrics, deposits the liner layers, over- fills the structure with metal, and then the overburden is removed by a planarizing chemical mechanical polish. This procedure has number of significant manufacturing advantages such global planarization and the production of very regular topographies. However, dual damascene processes do produce quite severe topographies with high aspect ratio vias and complex three-dimensional (3D) geometries. These challenging structures must be coated with diffusion barriers and seed layers and filled with either Cu or Al. The complexity of the deposition processes used (predominantly sputtering technologies for barrier dep- osition and electroplating or CVD for fill) has produced a need for a modeling capability. Two key aspects present themselves as important to be modeled. One is the basic growth behavior of the film surface which should allow for an analysis of the film coverage over topography. This is important for barrier layer and seed applications and also for the determination of the quality