EUROPEAN WORKSHOP ON ON-BOARD DATA PROCESING (OBDP2021), 14-17 JUNE 2021 PERFORMANT AND FLEXIBLE ON-BOARD PROCESSING MODULES USING RECONFIGURABLE FPGAS Björn Fiethe 1 , Lei Jia 1 , Harald Michalik 1 , Jamin Naghmouchi 1,2 1 IDA, TU Braunschweig, Hans-Sommer-Str. 66, 38106 Braunschweig, Germany 2 iTUBS mbH, Wilhelmsgarten 3, 38100 Braunschweig, Germany E-mail: fiethe@ida.ing.tu-bs.de ABSTRACT Current and future space missions demand sophisticated on-board data processing functionalities, while low resources consumption remains a constraint. Using in- flight dynamically reconfigurable FPGAs allows enhancement of on-board processing with unprecedented levels of flexibility, enabling the adaptation of the system regarding functional and fault- tolerance requirements, subjects to change during mission lifetime. After having demonstrated the usage of in-flight reconfigurability for SRAM-based FPGAs for the PHI instrument on Solar Orbiter (SO/PHI), we have developed a universal modul for high performance on-board data processing, based on cPCI Serial Space standard and state-of-the-art Xilinx Zynq Ultrascale+ MPSoC device on a single board (3U) for maximum flexibility. For improved reliability against SEEs, additional measures have been implemented, including a dedicated DDR3 memory error correction. This module is being used within the H2020 project S4Pro, which investigates how to combine state-of-the-art industrial computing technologies and space qualified embedded computing platforms in order to optimize the data processing chain and support the next generation of data intensive missions. A derivate version based on Xilinx XQRKU060 Space-grade FPGA provides dedicated connections for an external rad-hard reconfiguration engine, supporting different types of reconfiguration and scrubbing. 1. INTRODUCTION Current and future low-Earth orbit (LEO) space missions, such as Earth observation and 5G satellite communication, produce large amount of data that needs to be transferred, processed, and further downlinked. The same is true for deep space scientific missions, which suffer from very limited telemetry data rate. Both types of missions demand sophisticated on- board data processing functionalities, while low resources consumption remains a constraint. Thus, in- flight reconfigurable architectures are mandatory. Using dynamically reconfigurable radiation-tolerant FPGAs allows enhancement of on-board processing with unprecedented levels of operational flexibility. Dynamic reconfiguration during flight enables the adaptation of the system regarding functional and fault-tolerance requirements, improving both, performance and maintenance. This is necessary to handle very high data rates, extract and process final physical values by an autonomous, intelligent, and reliable application already on-board the spacecraft, and adapting itself to changing mission needs. The benefits of such an adaptable processing platform are a superior data yield and a reduced risk of a total instrument loss. An additional advantage of adaptability is the possibility to time-share resources for a more efficient hardware and power utilization, when dedicated functions are not necessary at the same time. Compared to general-purpose processors (GPPs), FPGAs offer a high processing performance combined with a low power consumption. FPGAs combines the performance of a hardware implementation with the flexibility of software realisation. 2. FIRST SCIENTIFIC MISSIONS We have already demonstrated the successful usage of SRAM-based FPGA devices for scientific instruments with e.g. the Venus Monitoring Camera (VMC) on Venus Express mission launched 2005. VMC was operational for more than 7 years with only a few numbers of resets due to Single Event Effects (SEEs), even fewer than have been expected. However, the reconfigurability was only used during the development phase on ground and no support for in-flight reconfiguration was built-in. For instrument control and data processing of the PHI instrument on the Solar Orbiter mission (SO/PHI), we have partially adapted results of the ESA study for a Dynamically Reconfigurable Processing Module (DRPM) and implemented a flexible, in-flight reconfigurable, power efficient, and radiation tolerant processing module based on Xilinx Virtex-4 SRAM- based FPGAs. Additionally, the module is equipped with a rad-hard processor and a one-time programmable system supervisor FPGA. A detailed description of the PHI DPU architecture is given in [1],[2]. The very