Performance a junctionless tran 1,2 Nano Electronics an *email Abstract- In this report we present a comp of ultra short 3-D junctionless nanowire DGM using different high-k gate dielectric by virtu the device in Visual TCAD. The ultra short channel length of 20nm were simulated and pe I-V characteristics, transconductance etc. were found that HfO 2 has better steady state perfo dielectric owing to better control of the chann and Si 3 N 4 . Index Terms- Junctionless DGMOS nanow High-k gate dielectric; 3-D virtual fabrication. I. INTRODUCTION In the recent years, with the contin CMOS technology, the interaction between processes and the device characteristics h become relevant to circuit designers. The n less transistors has emerged, to meet the stron have been arriving due to the shrink dimensions to fulfil Moore’s rule. As size o are reducing it resulted in some serious short [1], drain-induced barrier lowering (DIB important limitation to the performance of MOSFETs [2]–[6]. As the channel length does the oxide thickness. But beyond a m thickness, the leakage current increases. If h materials can replace SiO 2 , this limitation reduced [7], [8]. Unlike conventional MOSFETs, junctions less transistor do junctions. The source, drain and channel doped with homogeneous doping polarity. I advantages such as flexibility in the fabri nearly ideal sub threshold slope, high O ratio, low S/D series resistance and smal barrier lowering. Here we have considered structure and ignored the asymmetries and analysis as discussed in [5], [9]–[11] for simp In this paper, effects of scaling the gat replacing the SiO 2 by high-K materials conventional junctionless DGMOS nano (DGMOS NT) has been studied by computational theory and checking its va results simulated by Cogenda Visual TCA powerful TCAD tool. Use of HfO 2 as the H proves beneficial and the improvement characteristics is established in this paper SiO 2 . II. STRUCTURE OF JL TRAN The 3D structure of one of the junctionle Parameters Abbreviation Dimensions Gate Length L g 20nm Gate Width L w 20nm Silicon Thickness Tsi 10nm Doping Concentration Nd 10×10 19 /cm -3 Oxide Thickness Tox 2nm Oxide Material SiO 2 , Si 3 N 4 and HfO 2 3.9, 7.5 and 25 (Dielectric Const) analysis of ultra short nsistors with high-k gat N. Bora 1 *, R. Subadar 2, nd VLSI Design Laboratory, Department of E & C Eng NEHU, Shillong, India l – nbora@nehu.ac.in/nipankabora@gmail.com parative analysis MOS transistors ually fabricating t devices having erformances like e analysed. It was ormances as gate nel over the SiO 2 wire transistors; nuous scaling of n manufacturing has increasingly need of junction ng demands that king of device of the transistors t-channel effects BL) being one f the nanoscale scales down so maximum oxide high-K dielectric is substantially junction based not have any l are uniformly It exhibits many ication process, ON–OFF-current ll drain-induced d the symmetric quantum effect plicity. te thickness and are studied. A owire transistor developing a alidity with the AD, which is a High-K dielectric of the device over Si 3 N 4 and NSISTOR ess double-gate MOSFET designed by HfO simulation is shown in Fig 1 used to design the structure. is used throughout the n-type doped (N d =1×10 20 cm -3 ) silico Silicon layer is used as a gat the metal layer above the prominent gate dielectrics or and HfO 2 are used for compar Fig 1: Simulation diagram The structural dimensions simulations are shown in Tab Parameters A Dimensions Gate Length L g 20nm Gate Width L w 20nm Silicon Thickness Ts 10nm Doping Concentration N 10×10 19 /cm -3 Oxide Thickness To 2nm Oxide Material Si an 3.9, 7.5 and 25 (Dielectric Const) Ta A simplified device structure removing the buried oxid interpretation. All devices DGMOS te dielectric gineering O 2 as gate dielectric used in 1. Cogenda Visual TCAD tool is . Uniform doping concentration e junctionless transistor. Highly on substrate is used. N type poly te material Aluminum is used as e wires. Three different most r insulators namely SiO 2 , Si 3 N 4 rison. m of Junctionless DGMOS NT and parameters used during ble 1. Parameters Abbreviation Dimensions Gate Length g 20nm Gate Width w 20nm Silicon Thickness si 10nm Doping Concentration Nd 10×10 19 /cm -3 Oxide Thickness ox 2nm Oxide Material iO 2 , Si 3 N 4 nd HfO 2 3.9, 7.5 and 25 (Dielectric Const) able 1 e in Fig 2 shows the structure by de, Al, and wires for better are being simulated by using