Analog Integrated Circuits and Signal Processing, 24, 59±71, 2000 # 2000 Kluwer Academic Publishers. Manufactured in The Netherlands. Considerations about Nanoelectronic GSI Processors JOSE Â CAMARGO DACOSTA,* JAAP HOEKSTRA,{ MARTIJN J. GOOSSENS, CHRIS J. M. VERHOEVEN AND ARTHUR H. M. VAN ROERMUND The Electronics Research Lab, Delft University of Technology, NL2628 CD 4 Delft, The Netherlands Email: j.hoekstra@its.tudelft.nl. *On leave from Department of Electrical Engineering, Universidade de Brasilia, Brasilia, DF, Brasil Email: camargo@ene.unb.br. Received June 19, 1998; Accepted October 20, 1998 Abstract. According to recent studies, the basic technologies presently adopted by the semiconductor industry for memory and processor fabrication should attain limits imposed by the laws of physics around the year 2010. Nanoscale sized devices like single-electron transistors appear as a highly promising option to replace conventional devices by that time. In this study, considerations about the realization of a GSI processor, based upon nanoelectronic devices, are presented. Key Words: SET transistor, nanoelectronics, GSI processor, analog neural networks 1. Introduction The evolution of the semiconductor industry, as predicted by the S.I.A. roadmaps, [1], shall lead to transistor's minimum feature sizes below 0.07 micron by the year 2010. A serious questioning appears when further reductions on device's dimensions are con- sidered. At smaller dimensions the device's behavior is ruled by quantum mechanics [2], which can result in modi®cations of its electrical characteristics. Besides that, the power dissipated by these ULSI transistors is too high to allow the realization of integrated circuits with about 10 11 devices per cm 2 [3]. Other relevant limiting factors are: high electric ®elds that can cause device breakdown, vanishing bulk properties and doping nonuniformities, shrinkage of depletion regions leading to short circuits due to tunneling between source and drain regions, shrinkage and unevenness of gates oxides leading to leakage and premature breakdown of these dielectrics [4]. The expected ®gures for 2010, like device densities of 64 G per DRAM chip (800 M for microcomputer) a power dissipation of 180 W, with a 0.9 V power supply, and a maximum clock rate of 1100 MHz may be not too far from the achievable limit. In fact, the predicted clock rate increase and supply voltage reduction factors in the period 1998±2010 are less than 3, while the memory density increase factor is around 250. The power dissipation increase factor is even smaller, only 1.8 for the same period [5]. Tables 1 and 2 present the forecasts for the main product and technological parameters according to the roadmap. Factors like the disturbance of device behavior due to second-order effects [6], the signal delays due to the interconnecting lines and the heat transfer limitations of the integrated circuits seem to be responsible for that situation. Additionally, for features sizes below 0.07 micron, the devices' behavior is in¯uenced, and sometimes determined, by the already mentioned quantum mechanical effects. As a result, the maintenance of the same evolution rate for the following decade (2010±2020), does not appear to be achievable with the simple development of today's major technologies and devices. Nanoscale sized devices [4] may become an extremely attractive option for the develoment of integrated circuits with dimensions and performance limits well beyond the ultimate roadmap projections. Among these devices, single-electron transistors [3,7] present as attractive features an extremely low