Charge Localization During Program and Retention in NROM-like Nonvolatile Memory Devices Etienne Nowak, Elisa Vianello*, Luca Perniola, Marc Bocquet, Gabriel Molas, Rabah Kies, Marc Gely, Gerard Ghibaudo # Barbara De Salvo, Gilles Reimbold, Fabien Boulanger CEA, LETI, MINATEC, F38054 Grenoble, France; Phone: +33 438 781836, E-mail: etienne.nowak@cea.fr *also with DIEGM, University of Udine, Via delle Scienze 208, 33100 Udine, Italy. # IMEP/INPG Grenoble, France 1. Introduction An alternative solution to standard Flash memories is represented by nitride-trap memories as SONOS or NROM memories. NROM in particular can be operated in 2-bit/cell mode using localized trapping in Si 3 N 4 film [1]. Therefore it can comply with the increasing demand of bit density. However these structures are facing retention issues at high temperature and a quantitative analysis of the charge dis- tribution during program and retention is required. Various techniques have been employed to deduce the distribution of trapped charges injected by channel hot electrons in the Oxide/Nitride/Oxide stack (ONO) of stan- dard NROM devices. Among them we find charge pumping technique [2], GIDL and substhreshold slope monitoring [3], or analyses based on the surface potential model [4] and the measure of reverse/forward programming windows ( / ; Fig. 1). In this work the method described in [4] will be used on experimental data in order to evaluate the trapped charge distribution in program and retention conditions. The lateral migration (i.e. inside the trapping layer) and vertical migration (i.e. charge loss) of the trapped charges during retention will be quantitatively evaluated. Other trapping layers such as Al 2 O 3 and HfO 2 are also investigated. 2. Samples Description and Methodology The devices under analysis are presented on Fig.2. The gate stack is composed by 5 nm tunnel SiO2 plus 6 nm charge trapping layers: Si 3 N 4 deposited by LPCVD or HfO 2 or Al 2 O 3 deposited by ALCVD at 350°C. Then, a 10 nm thick High Temperature Oxide (HTO) is deposited as top oxide plus N+ Si-poly gate. After gate etching, standard processing steps include NiSi silicidation. Using the method presented in [4], the charge density and the effective charged length are extracted (Fig.3), based on and measured during program and retention. 3. Results and Discussions - Fig. 4 shows that the program- ming dynamics are dependent on the trapping layers and this even for short programming pulses, as shown in [6]. However, as shown in Fig. 5 the location of the charge is independent of the material: indeed is equal to 40 nm for smaller than 10 13 cm -2 (stress time of the or- der of 0.01 s). This can be explained by the fact that all devices have the same junction profile thus they have iden- tical injection efficiency of accelerated carriers by the elec- tric field [3]. Then when reaches 1.4x10 13 cm -2 (stress time over 0.01 s), continue to increase (Fig. 4) due to the increase of (Fig. 5). Seemingly the traps over drain junction becomes saturated, thus newly injected charges can redistribute in the trapping layer farther from the junction. We conclude that the charge distribution be- havior during programming is similar for the three materi- als, even if the device with Si 3 N 4 shows the best capture efficiency during the programming dynamics. - Fig. 7 shows data retention charac- teristics of devices at 25°C and 125°C. In Fig. 8, the extrac- tion of and shows that the shift is only due to the lateral charge migration at low temperature (ex- cepted for Al 2 O 3 at 125°C, where the vertical charge loss is the dominant mechanism). We stress that at high tempera- ture (200°C) decreases mainly because of vertical electron loss (not shown here). To simulate the lateral mi- gration of the trapped charges the numerical resolution of 1D Drift-Diffusion system is adopted (Fig. 9-10). From Fig. 11 we notice that the diffusion process is negligible with respect to drift, and the drift of charged particles is found equal to (Fig. 11) with linearly dependent with and independent of the shape of the injected charge. corresponds to an effective mo- bility that includes the trap/detrap process plus the drift in the conduction band [7]. Fig. 12 quantifies the lateral mi- gration of trapped charges for Al 2 O 3 , HfO 2 and Si 3 N 4 . The lateral migration follows a logarithmic law and the lowest drift is observed for Si 3 N 4 . 4. Conclusions In this paper, we have quantified the localization of the charges during programming and retention in NROM-like devices, based on experimental measurements (in particular of and ) and a surface potential model [4]. It ap- pears that during programming the charge is injected on a 40nm-length region in the trapping layer, with a charge density up to 1.4x10 13 cm -2 . Then the injected charge den- sity saturates and the trapped charge region broadens. Dur- ing retention, the lateral migration of the charge appears to be the dominant mechanism of the shift at room tem- perature. We have been able to quantify this shift based on a 1D drift model (diffusion being negligible). References [1] B. Eitan et al, IEEE EDL, vol. 21, n°11, 2000, pp. 543-545. [2] A. Furnemont et al, Proc. IEEE NVSMW, pp. 66-67, 2006. [3] E. Lusky et al IEEE TED, Vol. 51, No. 3, 2004, pp.444-451. [4] L. Perniola et al, IEEE IEDM Tech. Dig., 2005, pp. 857-860. [5] A. Furnemont et al., IEEE IEDM Tech. Dig., 2006. [6] T.Sugizaki et al., VLSI Tech Dig., 2003,pp.27-28. [7] E.Vianello et al., ESSDERC, 2008,pp.107-110. -152- Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials, Sendai, 2009, pp152-153 G-2-2