NBTI and hot carrier effect of SOI p-MOSFETs fabricated in strained Si SOI wafer Yong Woo Jeon a , Dae Hyun Ka a , Chong Gun Yu a , Won-Ju Cho b , M. Saif Islam c , Jong Tae Park a, * a Department of Electronics Engineering, University of Incheon, #177 Dohwa-Dong Nam-Gu, Incheon 402-749, Republic of Korea b Department of Electronic Materials Engineering, Kwangwoon University, #447-1 Wolgye-Dong Nowon-Gu, Seoul, Republic of Korea c Department of Electrical and Computer Engineering, University of California, Davis, CA, USA article info Article history: Received 10 June 2009 Available online 4 August 2009 abstract Comparative study on NBTI and hot carrier effects of p-channel MOSFETs fabricated by using strained SOI wafer and unstrained SOI wafer has been performed, respectively. It is observed that NBTI and hot carrier degradation are more significant in strained SOI devices compared with unstrained SOI devices. Since the devices fabricated in strained SOI wafer are SiGe free strained devices, the more generation of interface states during gate oxidation is the main cause for enhanced NBTI and hot carrier degradation in strained SOI devices. Ó 2009 Elsevier Ltd. All rights reserved. 1. Introduction Recently a strained Si MOSFET has gained significant attention due to its enhancement in the mobility and device performance. In order to realize advantages of strained Si on insulator, two ap- proaches have been developed. The first approach is the growth of Si epitaxial layer on the relaxed SiGe layer. The second approach is bonding the strained Si layer directly to the buried oxide (BOX) using SMART-CUT technology. It is known that the second ap- proach has advantages over the first approach because the total semiconductor thickness over the insulator becomes a critical con- straint for short channel effects [1]. Due to the enhanced impact ionization, a reduction of band gap energy, and Ge out-diffusion during gate oxidation, the hot carrier degradation is more significant in strained devices than unstrained devices, although the potential barrier between Si and SiO 2 in- creases [2,3]. Due to Ge out-diffusion during gate oxidation, NBTI induced threshold voltage shift of strained devices is also known more significant than that of unstrained devices [3,4]. In the case of SiGe free strained Si devices, it is expected that during gate oxi- dation the out-diffusion of Ge atoms in the stained Si toward the gate oxide is not serious, and thus it will not impact on the hot car- rier and NBTI effects. Although many studies on process technol- ogy and performance characterization of SiGe free strained Si devices [1,5], there is no study on the reliability study within our knowledge. The purpose of this work is to confirm that the enhanced degra- dation of SiGe free strained SOI (sSOI) devices is mainly influenced by the strain-induced interface state generation during gate oxida- tion process. Comparative study on NBTI and hot carrier effects of p-channel MOSFETs fabricated by using sSOI wafer and unstrained SOI wafer has been performed, respectively. 2. Device fabrication and measurement The sSOI wafers were fabricated by bonding the strained Si layer directly to the buried oxide (BOX) using SMART-CUT technology. Fig. 1 shows the schematic view of process sequences for the fab- rication of sSOI wafer. The strained p-type Si layer with resistivity of 10 X-cm epitaxially grown on a relaxed Si0.8Ge0.2 film, result- ing in biaxial tensile strain, was transferred to an oxidized p-type (1 0 0) Si wafers using hydrogen-induced layer transfer method. The strained Si layer with a thickness of 40 nm was obtained using CMP process. After the gate oxide growth of 8 nm, a Phosphorus doped poly-Si was deposited. Then, the source and drain region were formed using plasma doping process. For comparison, unstrained p-channel MOSFET was fabricated using SOI wafer with same process condition of sSOI devices except the BOX thickness which was 200 nm. The gate length and width of devices are 2 and 20 lm, respectively. NBTI stress was applied with gate electrode held at a constant negative bias of V G  V TH = 5.1 V under temperature between 50 °C and 125 °C while the source and drain electrodes were grounded. A conventional SMS technique was performed to characterize the NBTI induced device degrada- tion. In order to characterize the hot carrier effects, typical stress drain voltage and stress time were 5.8 V and 1 h. The stress gate voltage was varied from 0.0 V to 1.5 V. 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2009.06.015 * Corresponding author. Tel.: +82 32 770 8445; fax: +82 32 770 2371. E-mail address: jtpark@ioncheon.ac.kr (J.T. Park). Microelectronics Reliability 49 (2009) 994–997 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel