Electrical properties of WSi 2 nanocrystal memory with SiO 2 /Si 3 N 4 /SiO 2 tunnel barriers Ki Bong Seo a , Dong Uk Lee a , Seung Jong Han a , Eun Kyu Kim a, * , Hee-Wook You b , Won-Ju Cho b a Quantum-Function Spinics Laboratory, Department of Physics, Hanyang University, Seoul 133-791, Republic of Korea b Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Republic of Korea article info Article history: Received 19 August 2009 Received in revised form 20 September 2009 Accepted 20 September 2009 Available online 5 December 2009 Keywords: WSi 2 Nanocrystals Engineered tunnel barrier Nonvolatile memory device VARIOT abstract Nonvolatile memory devices using the WSi 2 nanocrystals on variable oxide thickness tunnel barrier com- posed of SiO 2 /Si 3 N 4 /SiO 2 (ONO) layers were fabricated and their electrical properties were evaluated. The WSi 2 nanocrystals with diameter of 2.5 nm and density of 3.6 Â 10 12 cm À2 were formed by using radio- frequency magnetron sputtering in the argon ambient and post-annealing process. In the device with 7- nm-thick ONO tunnel barrier, the threshold voltage shifts due to the memory effect of nanocrystals were observed about 1.6 V under +8 V/À10 V program/erase (P/E) voltages for 500 ms and maintained about 1.0 V after 10 6 s. The P/E speeds of this device were 100 ms with 1.0 V memory window. These results indicate that the ONO tunnel barrier with 7-nm-thickness provides an effective tunneling thickness for the fast P/E speeds and comparative physical thickness for long charge retention characteristic in nonvol- atile memory devices. Ó 2009 Elsevier B.V. All rights reserved. 1. Introduction The nanocrystal based memory has been introduced as a replacement for the conventional flash memory devices. Because it has discrete nanocrystals as a charge storage node instead of a continuous polycrystalline silicon floating gate, this structure effectively prevents the leakage current from nanocrystals to sub- strate and allows a thinner tunnel oxide thickness, smaller opera- tion voltage, faster programming/erasing (P/E) speed, and better reliability [1–3]. Among the different materials of nanocrystals, the metallic nanocrystal have several advantages, such as higher carrier confinement, higher density of states, and larger work func- tion [4,5]. Nevertheless, few kinds of metal can be used in current semiconductor industry process because the metal atoms easily diffuse into the oxide layer during thermal annealing process. For these reasons, the metal silicide nanocrystals have been studied for the charge storage node of nanocrystal memory device [6]. The metal silicide nanocrystals have metallic and silicide proper- ties, simultaneously. The metallic properties of metal silicide nano- crystals leads to higher density of state and work function, stronger coupling between the nanocrystals and channel region. Further- more, the silicide properties of metal silicide nanocrystals have a better thermal stability and compatibility with current semicon- ductor industry process. Especially, the WSi 2 has a large work function of 4.8 eV, good thermal stability, and chemical stability with Si atom [7–9]. Therefore, the nanocrystal memory devices with the WSi 2 nanocrystals are expected to have a good electrical performance and smaller diffusion problem than metal nanocrys- tals because of their good thermal stability. However, the trade-off between P/E speeds and charge reten- tion characteristics also exist in the nanocrystal memory devices. The conventional SiO 2 tunnel barrier cannot be scaled below 7– 8 nm due to the degradation of charge retention characteristics [10]. To overcome the limitations of the conventional SiO 2 tunnel barrier, the variable oxide thickness (VARIOT) tunnel barrier has been introduced as tunnel barrier of nonvolatile memory device (NVM) [11]. The VARIOT dielectric consists of two layer dielectric stack with a low-k/high-k dielectric combination or three layer stack with a low-k/high-k/low-k combination. When a bias is ap- plied to VARIOT stack, the effective tunneling thickness becomes equal to (or shorter than) the thickness of the first dielectric layer because of the electric field is much higher in the low-k layer than the high-k layer. In contrast, when a bias is not applied, the stored charges are difficult to tunneling back to the substrate through the multi layered tunnel barrier due to their thick total physical thick- ness [12,13]. For these reasons, the VARIOT dielectrics are utilized as a tunnel barrier instead of the conventional SiO 2 tunnel barrier for the fast P/E speeds and long retention time of NVM devices. In this study, we utilized a VARIOT tunnel barrier composed of SiO 2 /Si 3 N 4 /SiO 2 layers to improve the P/E speeds and retention characteristics of WSi 2 nanocrystal memory devices. Then, their 1567-1739/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.cap.2009.12.002 * Corresponding author. Tel.: +82 2 2290 0914; fax: +82 2 2295 6868. E-mail address: ek-kim@hanyang.ac.kr (E.K. Kim). Current Applied Physics 10 (2010) e5–e8 Contents lists available at ScienceDirect Current Applied Physics journal homepage: www.elsevier.com/locate/cap