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DAC'11, June 5-10, 2011, San Diego, California, USA Copyright © 2011 ACM 978-1-4503-0636-2/11/06...$10.00 Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C. lcw@sscas.ee.ncku.edu.tw; jmlin@ee.ncku.edu.tw; chew@livemail.tw; gppo@sscas.ee.ncku.edu.tw; soon@mail.ncku.edu.tw ABSTRACT One of the most important issues during the analog layout phase is to achieve accurate capacitance ratios. However, systematic and random mismatches will affect the accuracy of the capacitance ratios. A common-centroid placement is helpful to reduce the systematic mismatch, but it still needs the property of high dispersion to reduce the random mismatch [10]. To deal with this problem, we propose a simulated annealing [15] based approach to construct a common-centroid placement which exhibits the highest possible degree of dispersion. To facilitate this framework, we first propose the pair-sequence representation to represent a common-centroid placement. Then, we present three operations to perturb the representation, which can increase the degree of dispersion without breaking the common-centroid constraint in the resulting placement. Finally, to enhance the efficiency of our simulated annealing based approach, we propose three techniques to speed up our program. The experimental results show that our placements can simultaneously achieve smaller oxide-gradient- induced mismatch and larger overall correlation coefficients (i.e., higher degree of dispersion) than [10] in all test cases. Besides, our program can run much faster than [10] in larger benchmarks. Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids – Layout, Placement and routing General Terms: Algorithms, Design Keywords: Analog placement, capacitor array 1. INTRODUCTION The key performance of many analog integrated circuits (ICs) is related to the accuracy of capacitance ratios [3, 4, 10], such as analog-to-digital converters and switched-capacitor circuits [2]. Among these circuits, a successive-approximation-register (SAR) analog-to-digital converter (ADC) has attracted more attention recently due to its low power consumption (see Figure 1), and it is widely used in biomedical chips or portable/battery-powered instruments. One of the most important components in the SAR ADC is a capacitor array, which contains a set of capacitors C 1 , …, C n+1 and these capacitors have to satisfy a predefined capacitance ratio (i.e., C 1 = C 2 , C i+1 = 2C i , i = 2, …, n). A capacitor array is considered matched if its capacitance ratio exactly meets the predefined value. The linearity of the SAR ADC is highly related to the matching of the capacitor array. A well-matched capacitor array may become mismatched after IC manufacturing. The causes of mismatch in IC fabrication process can be divided into two categories: systematic mismatch and random mismatch [3, 4]. We illustrate each of them in the following: In the category of systematic mismatch, mechanisms have equal effects on each device. Thus, if two devices have identical layout size, they suffer the same percentage of difference from the mechanisms, which implies that the two devices still keep matched. Therefore, given a set of devices with different layout sizes, designers prefer to divide every device into several identical-layout-size sub-devices to achieve matching. However, the presence of process gradients also causes systematic mismatch [5]. If two devices have identical layout size but they are placed far away from each other in a layout, they would experience unequal magnitude of effects due to the process gradients and thus exhibit mismatch. Therefore, for a set of devices which require matching, they should be placed close to each other in a layout. Further, these devices should exhibit symmetry in the layout to average the effects induced by process gradients. In order to reduce systematic mismatch, designers usually adopt a common- centroid layout structure [1] to achieve these considerations. On the other hand, random mismatch is caused by statistical fluctuations in processing conditions or material properties. Since these fluctuations are random mechanisms, the sub-devices of each device should be distributed throughout a layout as uniformly as possible to reduce random mismatch, which means that the sub-devices should exhibit the highest possible degree of dispersion in a layout [10]. Figures 2(a) and 2(b) show two placements for a capacitor array according to different layout considerations. The capacitor u 4 u 4 u 4 u 3 u 3 u 4 u 4 u 4 u 4 u 3 u 3 u 2 u 1 u 3 u 3 u 4 u 4 u 3 u 3 u 4 u 2 u 3 u 3 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 3 u 3 u 3 u 4 u 4 u 3 u 3 u 3 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 3 u 3 u 4 u 4 u 4 u 4 u 3 u 3 u 2 u 1 u 3 u 3 u 4 u 4 u 3 u 3 u 4 u 2 u 3 u 3 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 3 u 3 u 3 u 4 u 4 u 3 u 3 u 3 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 3 u 3 u 2 u 3 u 4 u 4 u 4 u 4 u 3 u 4 u 4 u 1 u 4 u 3 u 4 u 4 u 4 u 3 u 3 u 2 u 3 u 4 u 4 u 4 u 4 u 3 u 3 u 4 u 4 u 3 u 4 u 3 u 4 u 4 u 3 u 4 u 4 u 4 u 4 u 3 u 4 u 3 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 3 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 3 u 3 u 2 u 3 u 4 u 4 u 4 u 4 u 3 u 4 u 4 u 1 u 4 u 3 u 4 u 4 u 4 u 3 u 3 u 2 u 3 u 4 u 4 u 4 u 4 u 3 u 3 u 4 u 4 u 3 u 4 u 3 u 4 u 4 u 3 u 4 u 4 u 4 u 4 u 3 u 4 u 3 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 3 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 u 4 (a) (b) Figure 2. Two different placements for a capacitor array. The unit capacitors denoted by u 3 are colored in gray for a clearer exhibition of different placement styles. (a) A common-centroid placement is good for reducing systematic mismatch. (b) The placement [10] exhibiting a higher degree of dispersion is better for reducing random mismatch. SAR Logic + − C n+1 C 1 C 2 C 3 C n V ref V in CLK B 1 ~B n Capacitor array (C 1 =C 2 , C i+1 =2C i , i=2~n) SAR Logic + − C n+1 C 1 C 2 C 3 C n V ref V in CLK B 1 ~B n Capacitor array (C 1 =C 2 , C i+1 =2C i , i=2~n) Figure 1. Architecture of an n-bit SAR ADC. The linearity of the SAR ADC is highly related to the matching of the capacitor array. 528 29.3