This work is licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. ech T Press Science Computers, Materials & Continua DOI: 10.32604/cmc.2022.023934 Article Design of Low Power Transmission Gate Based 9T SRAM Cell S. Rooban 1 , Moru Leela 1 , Md. Zia Ur Rahman 1 , *, N. Subbulakshmi 2 and R. Manimegalai 3 1 Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, 522502, India 2 Department of Electronics and Communication Engineering, Francis Xavier Engineering College, Tirunelveli, Tamil Nadu, 627003, India 3 Department of Computer Science and Engineering, PSG Institute of Technology and Applied Research, Coimbatore, Tamil Nadu, 641062, India *Corresponding Author: Md. Zia Ur Rahman. Email: mdzr55@gmail.com Received: 27 September 2021; Accepted: 30 December 2021 Abstract: Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consump- tion is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary com- ponents in fast mobile computing. Traditional SRAM cells are more energy- consuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and bet- ter writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed. Herein, an ST inverter with a single bit-line design is used to attain the high read stability. A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter. The multi- threshold complementary metal oxide semiconductor (MTCMOS) technique is adopted to reduce the leakage power in the proposed single-ended TG- ST 9T SRAM cell. The proposed system uses a combination of standard and ST inverters, which results in a large read stability. Compared with the previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for write operations, respectively. Keywords: Bit-interleaving; low power; SRAM cell; schmitt trigger; transmission gate 1 Introduction As technology evolves each day, the important design constraints for transistor scaling are the speed and integrated density, while leakages and reliability issues degrade the overall device perfor- mances. Further scaling results in short-channel effects, and overcoming this effect has led to several