1336 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 12, DECEMBER 2008 Schottky Barrier N-Type Thin Film Transistors With Polycrystalline Silicon Channel and Er-Silicided Metallic Junctions Jin-Wook Shin, Chel-Jong Choi, Moongyu Jang, and Won-Ju Cho Abstract—N-type Schottky barrier thin film transistors (SB-TFTs) with polycrystalline silicon channel and metallic junctions were fabricated by using Er silicidation, and electrical structural properties were compared to conventional TFTs with phosphorous-doped source/drain regions. The performances of SB-TFTs are better than that of the conventional TFTs. A forming gas annealing process leads to a great improvement in the characteristics of both devices. In particular, excellent electrical characteristics were obtained from the forming gas annealed SB-TFTs: the subthreshold swing of 180 mV/dec, the drive current of 1.47 × 10 −5 A, and the on/off current ratio of 5 × 10 6 . Index Terms—Er silicide, forming gas annealing (FGA), metal- lic junction, poly-Si Schottky barrier TFT (SB-TFT). I. I NTRODUCTION A S THE shrinkage of MOSFETs leads to the nanometer regime, the short-channel effect (SCE) is one of the major concerns to continue scaling for gaining better device performance and higher packing density. Recently, Schottky barrier MOSFETs (SB-MOSFETs) have been proposed as a viable candidate for nanometer-scale devices without sacrific- ing the productivity required by semiconductor device manu- facturers [1], [2]. Due to the replacement of impurity-doped Si in source/drain (S/D) regions with metallic silicides, the SB- MOSFETs have potential advantages over conventional devices such as high scalability, SCE immunity, and low extrinsic para- sitic resistance [3], [4]. Furthermore, since the S/D formation is carried out at low temperature, the metal gate and high-k technologies can be feasibly incorporated in SB-MOSFETs [5]. Manuscript received June 9, 2008; revised October 1, 2008. Current version published November 21, 2008. This work was supported in part by the Korean Government (MOEHRD, Basic Research Promotion Fund) under the Korea Research Foundation Grant KRF-2007-331- D00253 and in part by MKE/IITA under the IT R&D Program 2008-F-023-01 (Next generation future device fabricated by using nano junction). The review of this letter was arranged by Editor J. K. O. Sin. J.-W. Shin and W.-J. Cho are with the Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Korea (e-mail: chowj@ kw.ac.kr). C.-J. Choi is with the Department of Semiconductor Science and Tech- nology, Semiconductor Physics Research Center, Chonbuk National University, Jeonju 561-756, Korea (e-mail: cjchoi@chonbuk.ac.kr). M. Jang is with the U-terminal Research Team, Electronics and Telecommu- nications Research Institute, Daejeon 305-350, Korea. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2008.2007511 Generally, in order to realize a high device performance, the fabrication process of SB-MOSFETs is based on the ultrathin- body Si-on-insulator technology [6]. However, this approach leads to the increase in the cost of the starting material and, thus, the cost of the device. To overcome such limitations, the integration of SB-MOSFETs on the polycrystalline silicon (poly-Si) thin film on an insulator layer is more favorable. Furthermore, Schottky barrier thin film transistors (SB-TFTs) have potentials for system-on-glass applications due to low process temperature. In this paper, we describe a method to fabricate the Er-silicided n-type SB-TFTs with a poly-Si thin film as an active layer and demonstrate their electrical and struc- tural properties. Also, the effects of the forming gas annealing (FGA) process for improving the performance of TFTs are represented. II. EXPERIMENTAL PROCEDURE A 150-nm-thick SiO 2 film was thermally grown on the (100) p-type bulk Si substrate with a resistivity of 10–20 Ω · cm, followed by the deposition of the 90-nm-thick amorphous Si film using low pressure chemical vapor deposition (LPCVD). To crystallize the amorphous Si film, the furnace annealing was carried out at 600 ◦ C for 24 h in N 2 atmosphere. After patterning active regions, a 5-nm-thick SiO 2 film was grown by thermal oxidation at 900 ◦ C, on which a 100-nm-thick phosphorus-doped poly-Si film was deposited by LPCVD. The photolithography and dry etching were employed to de- fine a gate region. A sidewall spacer was formed by thermal oxidation at 900 ◦ C and subsequent dry etch processes. For forming Er-silicided metallic junctions, 50-nm-thick Er and 30-nm-thick tungsten (W) capping layers were sequentially sputter deposited, followed by rapid thermal annealing (RTA) at 500 ◦ C for 3 min in 1 × 10 −6 torr. Nonreacted Er and W capping layers were removed by a mixture of H 2 SO 4 and H 2 O 2 . For comparison, n-type conventional TFTs with phosphorus- doped S/D regions were fabricated using the same process conditions as described previously. S/D regions of n-type con- ventional TFTs were formed by the solid phase diffusion (SPD) of phosphorus silicate glass driven by RTA at a tempera- ture of 950 ◦ C for 30 s [7]. Phosphorus-doped poly-Si film and Al was used as gate electrode and S/D contact metal, respectively. Finally, SB-TFTs and conventional TFTs were postannealed at 450 ◦ C for 30 min in forming gas ambient (2% H 2 in N 2 ). 0741-3106/$25.00 © 2008 IEEE