A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication Systems J. H. Han1, A. T. Erdogan" 2, and T. Arslan1 2 'University of Edinburgh, School of Engineering and Electronics Edinburgh, EH9 3JL, Scotland, United Kingdom 2 Institute of System Level Integration, The ALBA campus Livingston, EH54 7EG, Scotland, United Kingdom j.hana-ed.ac.uk, Ahmet.Erdogana-ee.ed.ac.uk, Tughrul.ArslanOee.ed.ac.uk Abstract The authors present a reconfigurable soft-input soft-output (SISO) turbo decoder based on Max- Log maximum a posteriori (ML-MAP) algorithm implemented with a sliding window (SW) method. The turbo decoder is designed to support constraint lengths from 3 to 5 and synthesized to a 0.18um standard CMOS cell library. Power and area overheads for the reconfiguration are analyzed and compared with non-reconfigurable ASIC based turbo decoder for each constraint length. Our simulation results demonstrate that the reconfigurable architecture can be applied flexibly to various wireless communication systems without large power and area overheads. 1. Introduction Demand for turbo codes in wireless communication systems has been increasing since their appearance in the early 1990s, due to their outstanding performance in terms of bit error rate (BER) [1]. For this reason, they have been adopted by various wireless systems such as DVB-RCS, 3GPP UMTS, IEEE 802.16, and CCSDS [2]-[3]. Various turbo decoders have been developed to improve their performance at algorithm and architecture levels. A dual mode decoder for convolutional and turbo codes has also been introduced for multi-standard wireless communication systems [41. In order to correspond to different standards of wireless communication systems, a reconfigurable architecture is more suitable than an ASIC for better flexibility and more cost saving than a digital signal processor (DSP). There are many works in the literature researching reconfigurable Viterbi decoders for convolutional codes, e.g. [5]-[61. Whereas, there is not much work targeting reconfigurable turbo decoders. In this paper, we have implemented a reconfigurable turbo decoder based on ML-MAP with sliding window (SW) method. The application of turbo codes for constraint lengths larger than 5 is not reported in the literature to date. Therefore, the reconfigurable turbo decoder has been designed to support constraint lengths (K) from 3 to 5. For the reconfigurability, a mapping method for the forward and backward state metrc units (SMU) is presented to reallocate the generated state metrics for different constraint lengths. The SMU consists of a branch metric unit (BMU), a branch metric normalization unit (BMNU), add-compare-select (ACS) units, and mapping units (MAU). The log likelihood ratio (LLR) is computed by the LLR computation unit (LCU), which is efficiently implemented with a parallel 'compare' structure. Section 11 provides a brief introduction to turbo decoding. The reconfigurable architecture and its components are described in section 111. We demonstrate the comparisons of power consumption and area usage between the reconfigurable and ASIC turbo decoders in section IV and conclude with section V. II. TURBO DECODING ALGORITHM A. ML-MAP Algorithm The decoding process using the ML-MAP algorithm is performed by the forward and backward processes in order to compute all state metrics [71. These values are then used to compute the LLR values as shown by the following equation: L, =LI-L0 (1) Li = max [ak- i(St) + ck(s', s) + bk(s)] S'.:uk =+1 Lo = max [ak* 1(5') + c(s', s) +b(s)] where akq(s'), Ck(s's), and bk(s) represent branch, forward, and backward state metrics, respectively. The subscript k, s' and s denote time and trellis states. In equation (1), each of the metrics is represented as shown below: c,(s',s) = 1/2(Leui +Lxu + Lcy1uP) (2) ak(s) = mad4xak- (st) + ct(s', s)] bk(s') = max4bk+ 1(s) + ck(s', s)] (3) (4) where ck(s',s) is calculated by the a priori information (Le), the channel reliability value (L), input data (x and y,), the systematic bit (uks), and the parity bit (uk"). The Le is obtained from the LLR value computed in previous decoding process after 0-7803-9264-7/05/$20.002005 IEEE 247