296 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 4, APRIL 2010 107-GHz (Al,Ga)N/GaN HEMTs on Silicon With Improved Maximum Oscillation Frequencies Stefano Tirelli, Diego Marti, Student Member, IEEE, Haifeng Sun, Andreas R. Alt, Student Member, IEEE, Hansruedi Benedickter, Edwin L. Piner, and C. R. Bolognesi, Fellow, IEEE Abstract—We report high-speed fully passivated deep sub- micrometer (Al,Ga)N/GaN high-electron mobility transistors (HEMTs) grown on (111) high-resistivity silicon with current gain cutoff frequencies of as high as f T = 107 GHz and maximum os- cillation frequencies reaching f MAX = 150 GHz. Together, these are the highest f T and f MAX values achieved for GaN-based HEMTs implemented on silicon substrates to date. The perfor- mance reported here is competitive with recently published results for similar geometry high-performance passivated HEMTs on semi-insulating silicon-carbide substrates. Index Terms—AlGaN/GaN, high-electron mobility transistors (HEMTs), high-frequency performance, high-resistivity silicon (HR-Si), millimeter-wave transistors. I. I NTRODUCTION B ECAUSE of their unique set of physical properties, GaN-based high-electron mobility transistors (HEMTs) continue to be the focus of intense interest for high-power, wideband, and/or high-temperature applications [1], [2]. The key benefits of the (Al,Ga)N/GaN material system for mi- crowave and millimeter-wave HEMTs reside with their wide energy bandgaps and the high 2-D electron-gas-channel charge densities resulting from the spontaneous and piezoelectric polarizations associated with the lattice mismatch between (Al,Ga)N and GaN. In principle, this combination of charac- teristics enables rugged high-current-drive wideband transistors capable of operating at high voltages and temperatures. The fastest AlGaN/GaN HEMTs have historically been implemented on sapphire or on SiC substrates. Because of their affordability, ample supply, and good thermal conductivity at operating junction temperatures, high-resistivity silicon (HR- Si) substrates provide a low-cost solution for the realization of GaN-based power transistors in the lower microwave- frequency domain. Recent work established that GaN-based HEMTs grown on HR-Si also offer very good performances at millimeter-wave frequencies [3], [4], culminating with the realization of 100-nm-gate (Al,In)N/GaN HEMTs on HR-Si with cutoff frequencies of as high as f T = 102 GHz [5]. Manuscript received November 4, 2009; revised December 21, 2009. First published February 25, 2010; current version published March 24, 2010. The review of this letter was arranged by Prof. G. Meneghesso. S. Tirelli, D. Marti, H. Sun, A. R. Alt, H. Benedickter, and C. R. Bolognesi are with the Terahertz Electronics Group, Electromagnetic Fields and Microwave Electronics Laboratory, ETH-Zürich, 8092 Zürich, Switzerland (e-mail: colombo@ieee.org). E. L. Piner is with Nitronex Corporation, Durham, NC 27703 USA. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2009.2039847 We now report fully passivated (2 × 75)-μm-wide (Al,Ga)N/GaN HEMTs grown on HR-Si with gatelengths of 75 and 100 nm and source–drain spacings L SD of 2 and 1 μm. The devices demonstrate the highest f T ’s ever achieved on silicon substrates and much improved maximum oscillation frequencies f MAX in comparison with previous high f T devices built on silicon. Simultaneously maintaining a high f MAX /f T ratio while increasing f T is difficult because f MAX ∼ (f T /R G C DG ) 1/2 , implying that f MAX /f T should scale as ∼ (f T ) −1/2 . II. DEVICE FABRICATION T-gate HEMTs were fabricated on (Al,Ga)N/GaN HEMT layers from Nitronex Corporation. The epitaxial layers were deposited on a 100-mm float-zone refined HR-Si (111) sub- strate (10 kΩ · cm) [6]. The layer sequence consists of a nucle- ation/transition layer, a 1.7-μm GaN insulating buffer/channel layer, and a 17.5-nm-thick Al 0.26 Ga 0.74 N barrier followed by a 2-nm GaN cap. The material showed improved mobilities (∼1500 cm 2 /V · s) and surface morphology (crack-free epi- layer surface) with respect to the layers used in [3], [8], and [11]. Mesa isolation and ohmic contacts were formed as de- scribed elsewhere [3], [5], but with a thinner Ti/Al/Au ohmic metal stack of 28/47/50 nm. Linear TLM postprocessed data revealed an ohmic contact resistance of 0.55 Ω · mm and a channel sheet resistance of 600 Ω/sq. No gate dielectric or recessing was used in this process. Gate electrodes were defined by a 30-kV e-beam lithography in a ZEP/PMGI/ZEP resist trilayer. Gates were centered in the source–drain gap with T-head sizes of 200 and 400 nm and footprints of 75 and 100 nm, respectively. The gate lift-off metallization consisted of a 25-/375-nm Ni/Au metal stack. The source–drain separation L SD was 2 and 1 μm for the 75- and 100-nm gate HEMTs, respectively. A 100-nm-thick PECVD SiN passivation layer was then deposited at 300 ◦ C. The SiN film was patterned for contact pad openings and RIE etched in an SF 6 plasma. Finally, Ti/Au was evaporated and lifted off for the overlay metallization on the ohmic and the gate contacts, as well as measurements pads. III. RESULTS AND DISCUSSION Fig. 1 shows representative I –V characteristics for (a) 75-nm and (b) 100-nm-gate transistors. The dc output characteristics were measured for the range V DS =[0 to 7] V with V GS =[0 to − 3.5] V in steps of −0.5 V. The maximum 0741-3106/$26.00 © 2010 IEEE