148 • 2017 IEEE International Solid-State Circuits Conference ISSCC 2017 / SESSION 8 / DIGITAL PLLs AND SECURITY CIRCUITS / 8.4 8.4 A 2.5ps 0.8-to-3.2GHz Bang-Bang Phase- and Frequency-Detector-Based All-Digital PLL with Noise Self-Adjustment Taekwang Jang 1 , Seokhyeon Jeong 1 , Dongsuk Jeon 2 , Kyojin David Choo 1 , Dennis Sylvester 1 , David Blaauw 1 1 University of Michigan, Ann Arbor, MI 2 Seoul National University, Seoul, Korea Digital PLLs are popular for on-chip clock generation due to their small size and technology portability. Variability tolerance is a key design challenge when designing such PLLs in an advanced CMOS technology. Environmental variations, such as mismatch, process, supply voltage, and temperature (PVT) perturb device characteristics and result in performance changes, such as DCO gain and noise. Another consideration is the wide range of operating modes in which modern digital circuits (e.g., processors) operate. For instance, a clock generator for a processor may produce a range of frequencies from tens of MHz to several GHz depending on required processor performance. In low-frequency mode, the power consumption is more pronounced than the noise. Therefore, we seek to design a PLL that is both insensitive to environmental variations, as well as reconfigurable to changing noise and power specifications. Conventional approaches [1-3] have focused on optimizing PLL loop bandwidth to minimize overall noise. In this way, the overall noise can be optimized within a given power level. However, with prior approaches, it was not possible to trade- off the power consumption with the noise specification. Furthermore, the period jitter, which is mostly governed by DCO noise, could not be optimized. A multiplying DLL (MDLL) is an attractive architecture to minimize integrated phase noise, but it suffers from limitations, such as a limited multiplication ratio and large peak-to-peak period jitter at the edge injection [4]. This paper introduces a nested frequency locked-loop (FLL) architecture, whose gain is accurately controlled by a capacitor ratio in order to keep the PLL bandwidth insensitive to variations. In addition, the noise of the FLL is independent of the delay cell, but dependent on a current reference so that the DCO noise is programmable independent of the oscillation frequency. A noise-detector block, using statistical characteristics of a bang-bang PFD (BBPFD) output, is employed to efficiently sense DCO noise. The PLL dynamically reconfigures the DCO noise from 2.5-15ps and self-adjusts its power from 1.7-5mW according to the noise specification. Figure 8.4.1 shows the conceptual schematic of an oscillator using switched capacitor-based frequency feedback [5]. The frequency generated by a voltage- controlled oscillator (VCO) is sensed as the effective resistance of a switched capacitor. A feedback current (I F ) is generated by regulating the effective resistance with M1 (Fig. 8.4.1 bottom left). Then, I F is compared with input current (I IN ), which is generated by regulating an on-chip resistor R 0 with M2. Finally, F OUT is locked to a frequency that equalizes I F to I IN . Assuming the voltages on R 0 and C SW are equal, the frequency becomes 1/R 0 C SW . The noise of the FLL is also calculated in Fig. 8.4.1. The sampling switch with on-resistance of R S generates noise whose power spectral density is (1). Due to the sampling operation, the noise is aliased and folded by the sub-sampling ratio, n. The equivalent current noise of the switched capacitor can be expressed as (4) and its fraction is delivered to M1 (5). Finally, the phase noise from the noise of the switched capacitor can be expressed by (6). As the VCO noise is high-pass filtered by the FLL loop bandwidth, the FLL output noise is dominated by the noise of R 0 and the switched-capacitor feedback circuit as in the following equation: L(f) = α 2 f 2 OUT (4kTγ + 4kT) / I IN V R f 2 Here k, T, γ, and V R are Boltzmann’s constant, temperature, transistor noise coefficient and voltage on R 0 and the switched capacitor. Also, α is the current division ratio at the branch of the source of M1 and M2. The phase noise of the proposed oscillator is inversely proportional to the input current, defined by V R /R 0 . Therefore, the key result is that the DCO phase noise can be reconfigured without impacting the oscillation frequency by changing R 0 and C SW , while maintaining a constant R 0 C SW product. In order to dynamically adjust DCO noise, a noise detector using statistical characteristics of a phase detector output is utilized, as shown in the block diagram of Fig. 8.4.2. Assuming a high resolution ΔΣ modulator, the DCO frequency is centered at M×F REF and toggles by K DCO (K P + K I ), which results in the limit cycle of the PLL. Therefore, the probability density function (PDF) of the phase error (φ err ) is composed of two Gaussian distributions of DCO noise separated by the phase limit cycle, as shown in the bottom left of Fig. 8.4.2. The shaded region of the PDF represents the possibility of generating an inverted BBPFD output owing to DCO noise. The presence of consecutive 1s or 0s at the output of the BBPFD is an indication of that possibility (since, in the absence of noise, the BBPFD output should alternate between 0 and 1 every reference cycle). The noise detector counts the number of consecutive 1s and 0s and accumulates the results over N reference cycles. The output of the noise detector, N CNT , is compared with the input noise reference, N REF , and the DCO noise controller adjusts R 0 and C SW to lock N CNT to N REF . An example transient locking process is shown in Fig. 8.4.3. First, the phase and frequency of the proposed PLL locks to the target by tuning C SW with C CON . After phase lock is achieved, the noise-locking loop is enabled and invokes a binary search for the R 0 , C SW combination that matches N CNT to N REF . The amplifiers shown at bottom right of Fig. 8.4.2 set V GP and V GN . Their bandwidth is smaller than the PLL loop bandwidth so that their noise is filtered out by the PLL. The frequency tuning curve of the proposed DCO is highly linear and invariant to supply and temperature changes since DCO frequency is explicitly defined by R 0 and C SW . Fig. 8.4.4 shows the frequency tuning curve of the proposed DCO compared with the conventional DAC+VCO approach. Due to the non-linear frequency tuning curve of a current-starved VCO, the frequency tuning curve of DAC+VCO is highly non-linear despite of the linearity of the DAC. On the other hand, the proposed DCO provides a highly linear frequency tuning curve under a wide range of PVT variation, which helps to keep the loop bandwidth constant and enables accurate noise locking. A test chip was fabricated in 28nm FDSOI with area of 0.049mm 2 . The left of Fig. 8.4.5 shows the reconfiguration of phase noise when changing the power consumption from 1.7-5mW, yielding an integrated jitter ranging from 15-2.5ps. The function of the noise detector is validated by changing the DCO gain and noise as shown Fig. 8.4.5 (right). The increase in proportional path gain (C PROP ) increases φ lmt and reduces N CNT /N. The phase noise graph of the proposed DPLL is depicted in Fig. 8.4.5 (bottom). Fig. 8.4.6 presents the performance summary and comparison to prior digital PLLs that use a ring oscillator. The proposed digital PLL provides wide range of power and phase noise configurability, and shows a competitive figure-of-merit. Note that while some prior art employs a >200MHz frequency reference, which helps in filtering the DCO noise, the proposed work uses a more cost effective 50MHz reference. Acknowledgements: STMicroelectronics is gratefully acknowledged for IC fabrication. References: [1] G. Marzin, et al., "A Background Calibration Technique to Control Bandwidth in Digital PLLs," ISSCC, pp. 54-55, 2014. [2] J. Crossley, et al., "An Energy-Efficient Ring-Oscillator Digital PLL," CICC, 2010. [3] T. K. Kuan and S. I. Liu, "A Digital Bang-Bang Phase-Locked Loop with Automatic Loop Gain Control and Loop Latency Reduction," IEEE Symp. VLSI Circuits, pp. 138-139, 2015. [4] H. Kim, et al., "A 2.4GHz 1.5mW Digital MDLL Using Pulse-Width Comparator and Double Injection Technique in 28nm CMOS," ISSCC, pp. 328-329, 2016. [5] A. A. Abidi, "Linearization of Voltage-Controlled Oscillators Using Switched Capacitor Feedback," JSSC, vol. 22, no. 3, pp. 494-496, 1987. [6] C. W. Yeh, C. E. Hsieh and S. I. Liu, "19.5 A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise Cancellation," ISSCC, pp. 332-333, 2016. 978-1-5090-3758-2/17/$31.00 ©2017 IEEE