26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 61, NO. 1, JANUARY 2014 A Subthreshold Symmetric SRAM Cell With High Read Stability Roghayeh Saeidi, Student Member, IEEE, Mohammad Sharifkhani, Member, IEEE, and Khosrow Hajsadeghi Abstract—This brief introduces a differential eight-transistor static random access memory (SRAM) cell for subthreshold SRAM applications. The symmetric topology offers a smaller area overhead compared with other symmetric cells for the same stability in the read operation. Two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability at the expense of read operation delay. Thorough postlayout Monte Carlo worst corner simulations in 45-nm CMOS technology are conducted. The proposed cell operates down to 0.35 V with a read noise margin of 74 mV and a write noise margin of 92 mV. Under this condition, the read and write noise margins of the conventional six-transistor (6T) cell are 18 and 27 mV, respectively. The cell area is 1.57× the conventional 6T SRAM cell area in 45-nm design rules. Index Terms—Data stability, iso-area analysis, subthreshold static random access memory (SRAM). I. I NTRODUCTION T HE INCREASING number of transistor count in the static random access memory (SRAM) units and the surging leakage current of the MOS transistors in the scaled technolo- gies have made these units power hungry. Many applications, including biomedical and wireless sensor networks, require ultralow-power circuits for long-term operation. In recent years, in order to tackle the power consumption, supply voltages have been scaled to the subthreshold region, where the data stability of the SRAM cells is a major concern. In the sub/near-threshold region, the conventional six-transistor (6T) cell fails to operate because of the degradation in read stability and write-ability [1]. Fig. 1 illustrates the read operation challenge of the conven- tional 6T cell during a read access, where the raising voltage of node “QB,” from zero to ΔV , drives the input of the M2–M4 inverter and may destroy the stored data, particularly in the subthreshold region. Moreover, in order to have a successful write operation, a wider access transistor is desirable; however, increasing the width of the access transistors threatens the read stability by affecting the cell ratio. This calls for a tradeoff between the data stability during a read operation and the success of a write operation. Various bit cells with varying number of transistors (6T–10T) have been proposed to solve the stability problem of the SRAM Manuscript received December 29, 2012; revised May 2, 2013 and July 15, 2013; accepted October 31, 2013. Date of publication January 9, 2014; date of current version January 13, 2014. This brief was recommended by Associate Editor H.-J. Yoo. The authors are with the Department of Electrical Engineering, Sharif University of Technology, Tehran 11365-9363, Iran (e-mail: rosaeidi@ee. sharif.edu; msharifk@sharif.edu; ksadeghi@sharif.edu). Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2013.2291064 Fig. 1. (a) Conventional 6T SRAM cell during the read operation. (b) Conventional 8T cell. in the subthreshold region [2]. Most are based on breaking the tradeoff between the read and write operations by using a read buffer that isolates the read port from the internal nodes [3], [4]. However, they either require a large area or employ a single- ended read port, which results in a reduced read sensitivity. For example, as shown in Fig. 1(b), the conventional eight- transistor (8T) cell uses two stacked transistors, namely, M7 and M8, for read to eliminate the read operation disturbance. This cell, however, has a single-ended structure that makes sensing a challenge. Others modify the cell structure to isolate the read and write operation paths [5], [6]. Nevertheless, the area overhead (A.O.) of the extra transistors is seen as the main obstacle to the popularity of these configurations. This brief proposes a differential 8T (D8T) SRAM cell that operates in the subthreshold region and efficiently improves the read static noise margin (SNM). This D8T cell breaks the feedback loop of the cell during the read operation to guarantee the stability of the stored data. The rest of this brief is organized as follows. In Section II, the proposed D8T SRAM cell is explained. Section III presents the cell performance based on the simulation results. Section IV compares the minimum V DD and the leakage of the D8T cell with the conventional 6T and 8T cell designs under the iso-area condition. Finally, Section V concludes this brief. II. PROPOSED D8T SRAM CELL DESIGN Fig. 2 illustrates the circuit diagram of the proposed D8T cell during the read operation for QB =0 and Q =1. The proposed cell utilizes a differential sensing scheme and uses two additional nMOS switches, namely M7 and M8, which are placed between the storage nodes (Q2 and QB2) and the access nodes (output of cross-coupled inverters, Q and QB). M7 and M8 are controlled by the read wordline (RWL) signal, whereas the access transistors, namely M5 and M6, are controlled by the wordline (WL). The table under the circuit diagram shows the voltage levels of the WL and the RWL for different operational modes. In the hold mode, the RWL is kept at V DD to turn on the feedback loop of the cross-coupled inverters. Thus, the hold SNM of the D8T SRAM cell is similar to that of the 6T cell. 1549-7747 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.