Prognosis of NBTI Aging Using a Machine Learning Scheme Naghmeh Karimi * and Ke Huang † * Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ 08854 † Department of Electrical and Computer Engineering, San Diego State University, San Diego, CA 92182 Abstract—Circuit aging is an important failure mechanism in nanoscale designs and is a growing concern for the relia- bility of future systems. Aging results in circuit performance degradation over time and the ultimate circuit failure. Among aging mechanisms, Negative-Bias Temperature Instability (NBTI) is the main limiting factor of circuits lifetime. Estimating the effect of aging-related degradation, before it actually occurs, is crucial for developing aging prevention/mitigations actions to avoid circuit failures. In this paper, we propose a general-purpose IC aging prognosis approach by considering a comprehensive set of IC operating conditions including workload, usage time and operating temperature. In addition, our model considers process variation by using a calibration technique applied at the time of manufacturing. Experimental results confirms that our model is able to accurately predict the NBTI-related path delay degradation under various operating conditions. The proposed model is robust to process variations. I. I NTRODUCTION As aggressive scaling continues to push technology into smaller feature sizes, various design robustness concerns con- tinue to arise. Among them, degradation mechanisms such as Negative-Bias Temperature-Instability (NBTI), Hot-Carrier In- jection (HCI), and gate Oxide Breakdown (OB) have attracted enormous attention [1]–[3]. In practice, in advanced technolo- gies, electrical behavior of transistors eventually deviates from its original intended behavior. This deviation may degrade performance; and consequently, the chip suddenly fails to meet some of the required specifications [4], [5]. Performance degradation of an IC due to aging is influ- enced by the operating conditions of the circuit including temperature, voltage bias, and current density [6]. In particular, among aging mechanisms, NBTI has received the lion’s share of attention [7]. NBTI occurs when traps are generated at the Si-SiO 2 interface when a negative voltage is applied to a PMOS device [8]. It shifts the threshold voltage of the device during its lifetime, degrades the device drive current, and in turn degrades the circuit performance [9]. Although tremendous efforts have been invested to mitigate the aging effects, the effect of NBTI is still significant. In practice, as VLSI technology scales, NBTI significantly contributes in degrading circuit reliability [10], [11]. To mitigate NBTI- related performance degradation and to increase the reliability of circuits, several methods have been proposed in literature. Guard-banding, gate-sizing, voltage tuning (changing V dd and V th ), and body biasing are among the methods used in industry to reduce the rate of timing and functional errors induced by NBTI effects [12]. The effect of aging mechanisms can be analyzed and monitored at real time to project aging degradation in a circuit in a foreseeable future [13]. This method, so called aging prognosis, allows to proactively estimate the effect of degradation before it actually occurs, such that preventive actions can be put in place to avoid catastrophic consequences. In predicting aging induced degradations, a number of envi- ronmental factors should be considered, including workload, temperature, voltage variations, process variation, etc [14]. In this paper, we propose a general-purpose IC aging prognosis approach by taking into account a comprehensive set of IC operating conditions including workload, usage time, run-time temperature, etc. We show that the impact of IC aging on critical path delays can be accurately predicted using non-linear regression models. Moreover, we generalize our prediction model for circuits under process variation using a calibration technique applied at the time of manufacturing. Thus, the effect of process variation on aging prediction can be compensated. The rest of this paper is organized as follows. Section II presents a background on NBTI aging. Section III discusses the proposed aging prognosis method. Experimental Results and discussions are presented in Section IV. Conclusions and future directions are drawn in Section V. II. BACKGROUND ON NBTI AGING NBTI is one of the leading factors in performance degra- dation of digital circuits. In practice, a PMOS transistor expe- riences two phases of NBTI depending on its bias condition. The first phase, i.e., the stress phase, occurs when the transistor is on, i.e., when a negative voltage is applied to its gate. In the stress phase, positive interface traps are generated at the Si-SiO 2 interface. As a result, the magnitude of the threshold voltage of the transistor is increased. In the second phase, i.e., recovery phase, a positive voltage is applied to the gate of the transistor. In this phase, the threshold voltage drift induced by NBTI during the stress phase can partially “recover”. Threshold voltage drifts of a PMOS transistor under stress depend on the physical parameters of the transistor, supply voltage, temperature, and stress time. Figure 1 shows the threshold voltage drift of a PMOS transistor that is contin- uously under stress for 6 months as well as a transistor that is under stress and recovery every other month. As shown, the NBTI effect is high in the first couple of months but the threshold voltage tends to saturate for long stress times. In this paper, to evaluate the impact of NBTI on the per- formance of a circuit under stress, Synopsys HSpice MOSRA (MOS Reliability Analysis) [15] is deployed. 978-1-5090-3623-3/16/$31.00 ©2016 IEEE Authorized licensed use limited to: University of Maryland Baltimore Cty. Downloaded on June 14,2021 at 17:30:54 UTC from IEEE Xplore. Restrictions apply.