IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 11, NOVEMBER 2002 1969 Voltage- and Temperature-Dependent Gate Capacitance and Current Model: Application to ZrO n-channel MOS Capacitor Yang-Yu Fan, Renee E. Nieh, Jack C. Lee, Fellow, IEEE, Gerry Lucovsky, George A. Brown, Member, IEEE, Leonard Frank Register, and Sanjay K. Banerjee, Fellow, IEEE Abstract—Based on the energy-dispersion relation in each region of the gate-dielectric-silicon system, a tunneling model is developed to understand the gate current as a function of voltage and temperature. The gate capacitance is self-consistently calculated from Schrödinger and Poisson equations subject to the Fermi–Dirac statistics, using the same band structure in the silicon as used for tunneling injection. Franz two-band dispersion is assumed in the dielectric bandgap. Using a Wentzel–Kramer–Bril- louin (WKB)-based approach, direct and Fowler–Nordheim (FN) tunneling and thermionic emission are considered simultaneously. The model is implemented for both the silicon conduction and valence bands and both gate- and substrate-injected currents. ZrO NMOSFETs were studied through temperature-dependent - and - simulations. The extracted band gaps and band offsets of the ZrO - and interfacial-Zr-silicate-layer are found to be comparable with the reported values. The gate currents in ZrO -NMOSCAPs are found to be primarily contributed from the silicon conduction band and tunneling appears to be the most probable primary mechanism through the dielectric. Oscillations of gate currents and kinks of gate capacitance were observed near flat-band in the experiments. These phenomena might be caused by the interface states. Index Terms—High-K gate dielectric, leakage currents, MIS de- vices, MOSFETs, semiconductor device modeling, tunneling. I. INTRODUCTION S iO has been used as the gate dielectric because of its process advantages and good interface properties with silicon. As gate lengths have been reduced, the SiO thickness also has been reduced to maintain gate control over the channel. However, in the deep submicron regime, the direct tunneling current limits this scaling process [1]–[3]. In order to overcome this limitation, high-K (or high dielectric constant) materials are being introduced to achieve a greater physical thickness and thus reduce the direct tunneling current while retaining a low equivalent oxide thickness (EOT). Different materials such as ZrO and HfO have been shown [4]–[6] promise for transistor application. Owing to the com- Manuscript received April 2, 2002. This work was supported in part by Semi- conductor Research Corporation. The review of this paper was arranged by Editor C. C. McAndrew. Y.-Y. Fan, R. E. Nieh, J. C. Lee, L. F. Register, and S. K. Banerjee are with the Microelectronics Research Center, University of Texas at Austin, Austin, TX 78758 USA (e-mail: yyfan@mail.utexas.edu). G. Lucovsky is with the Department of Physics, North Carolina State Uni- versity, Raleigh, NC 27695 USA. G. A. Brown is with the International SEMATECH, Austin, TX 78741 USA. Digital Object Identifier 10.1109/TED.2002.804713 plex fabrication process of transistors, most studies have been conducted on MOSCAPs. The uncertainty of the material prop- erties, especially for the thin films, imposes another difficulty in terms of understanding the experimental results. In this work, through – and – simulations, the material properties of ZrO -NMOSCAPs are extracted in the accumulation region. High-K materials, not coincidentally, generally have smaller band gaps and smaller band offsets with silicon than SiO [7]. In addition to direct tunneling, Fowler-Nordheim (FN) tunneling can be important because of the smaller band offsets. The thermionic emission also needs to be considered for ma- terials with extremely small band offsets and for transistors in which hot carriers are of concern. Gate currents from the silicon conduction band and valence band may be nonnegligible at the same time. Furthermore, an interfacial layer is generally found between the high-K layer and the silicon substrate. These all impose difficulties in terms of understanding the experimental gate currents. With increasing normal fields as a result of high doping con- centrations and reduced EOTs, quantum confinement effects can no longer be neglected [8]–[11]. In this paper, we report a Wentzel–Kramer–Brillouin (WKB)-based gate current model that considers quantum confinement effects and is applied to the inversion and accumulation regions and both the conduction and valence band components. Direct, FN tunneling and thermionic emission are considered simultaneously. The gate capacitance has been used for extracting the EOTs [8]–[10], beyond which the capacitance-voltage be- havior should be modeled concurrently with current-voltage. The charge redistribution in the gate-dielectric-silicon struc- ture must be determined self-consistently by solving the Poisson-Schrödinger equations. The gate capacitance provides an experimental probe of the charge distribution at different gate voltages and this is key to modeling the gate current. Temperature-dependence study of gate currents and gate ca- pacitance of MOS capacitors with SiO shows this correlation: the temperature-dependent region of the gate capacitance, which is near the flat-band, is the same as that of the gate current [12]. Such temperature-dependence is attributed to temperature-dependence of the charge distribution or “supply function” instead of the temperature-dependence of the carrier transport in the SiO . In this work, the simultaneous agreement of gate capacitance and gate current simulation with experiment has been obtained. 0018-9383/02$17.00 © 2002 IEEE