Research Article Design of CDTA and VDTA Based Frequency Agile Filters Neeta Pandey, 1 Aseem Sayal, 2 Richa Choudhary, 2 and Rajeshwari Pandey 1 1 Department of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, India 2 Department of Electrical Engineering, Delhi Technological University, Delhi 110042, India Correspondence should be addressed to Neeta Pandey; n66pandey@redifmail.com Received 21 May 2014; Revised 3 November 2014; Accepted 3 November 2014; Published 23 December 2014 Academic Editor: Weisheng Zhao Copyright © 2014 Neeta Pandey et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Tis paper presents frequency agile flters based on current diference transconductance amplifer (CDTA) and voltage diference transconductance amplifer (VDTA). Te proposed agile flter confgurations employ grounded passive components and hence are suitable for integration. Extensive SPICE simulations using 0.25 m TSMC CMOS technology model parameters are carried out for functional verifcation. Te proposed confgurations are compared in terms of performance parameters such as power dissipation, signal to noise ratio (SNR), and maximum output noise voltage. 1. Introduction Te rapid evolution of wireless services has led to demand for one-fts-all “analog” front end solution. Tese services use diferent standards and therefore necessitate development of integrated multistandard transceivers as they result in reduction of size, price, complexity, and power consumption. Te parameters of integrated transceiver can be modifed in order to be able to adapt to the specifcations of each standard [1]. Practically, the designs employ either elements handling various standards in parallel or reconfgurable elements. Te frequency agile flter (FAF) [1–10] characterized by adjustment range, reconfgurability, and agility may be used in transceivers. Te term shadow flters is sometimes used in literature to refer to FAF [11, 12]. Te literature survey shows that a limited number of topologies of active FAF are available and are based on op-amp [1] and current mode active block [2, 3] and CMOS [4]. Tere is a wide range of current mode building blocks available in open literature. Among these blocks current diference transconductance amplifer (CDTA) [11] is most suitable for current mode signal processing owing to its low input and high output impedances, respectively. Te VDTA is yet another recently introduced building block which works on a principle similar to that of CDTA except that the input current diferencing unit is replaced by the voltage diferencing circuit. Many applications such as flters and oscillators based on CDTA and VDTA are available and have been reported in the literature [13–27] and references cited therein. Te main intention of this paper is to present CDTA and VDTA based frequency agile flter topologies. Te proposed flters are suitable for integration as these employ grounded capacitors and a resistor. Te paper is organised as follows. Te FAF implementation scheme is briefy reviewed in Section 2. Te CDTA based Class 0, Class 1, and Class 2 FAF are presented in Section 3. Section 4 deals with the realization of VDTA based Class 0, Class 1, and Class 2 FAF. In Section 5, nonideal analysis of flters is presented. Simulation results are provided in Section 6 to substantiate the proposed FAF topologies. Te performance characteristics of flter topologies are described in Section 7. Te paper is concluded in Section 8. 2. Implementation Scheme of FAF Te implementation scheme of frequency agile flter (FAF) [3] is briefy reviewed in this section. 2.1. Class 0 FAF. A classical second order flter with band pass ( BP ) and low pass ( LP ) outputs of Figure 1 is designated as Hindawi Publishing Corporation Advances in Electronics Volume 2014, Article ID 176243, 15 pages http://dx.doi.org/10.1155/2014/176243