Implementation Aspects of An Early Decision Decoder for LDPC Codes Anton Blad, Oscar Gustafsson, and Lars Wanhammar Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden, {antonb, oscarg, larsw}@isy.liu.se Abstract Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decod- ing data. In this paper, we propose an architecture for an early decision decoding algorithm. The algorithm signifi- cantly reduces the number of memory accesses. Simula- tion results show that the increased energy dissipation of the components is small compared to the reduced dissipa- tion of the memories. 1. Introduction Low-density parity-check (LDPC) codes were invented by Robert G. Gallager [1] in the early 60’s. However, despite excellent performance and a practical decoding algorithm, they were largely neglected for over 30 years until they were rediscovered by MacKay and Neal [2] in the mid 90’s. Since then, LDPC codes have been found to have performances comparable to, and in some cases exceeding, those of Turbo codes. The main problem in coding theory is to build a prac- tical and efficient decoder. The decoding algorithm for LDPC codes is inherently parallelizable, and thus suitable for communication at high speeds. However, the random structure of the codes limits the parallelizability, such that fully parallel decoders are not feasible for codes much longer than 1000 bits. In a partly-parallel architecture, the internal communication translates to large memories for interim storing of decoder data. A typical code with a length of 6000 bits might require up to a million memory accesses for the decoding of a sin- gle word. Other work indicates that up to 95% of the power is consumed in the memories [3], thus reducing the amount of memory accesses becomes an important con- cern, especially in low-power hand-held devices. Recently , the idea of early decision decoding was introduced [4]. The early decision decoding algorithm is a modification to the usual probability propagation algo- rithm. The idea is to exploit the different convergence rates of the bits, to deactivate computations for bits that are likely to be known. The result is a reduction of the amount of memory accesses. As a base for the proposed architecture, the partly-par- allel decoder architecture in [5] is used, although the algo- rithm is not locked to this particular architecture. The modifications are primarily in the variable node process- ing elements, where an additional memory is added to store for which bits the computations are disabled. The rest of this paper is organized as follows. Section 2 and 3 briefly describes low-density parity-check codes, and the sum-product decoding algorithm, respectively. In Section 4, early decision decoding is introduced. Section 5 describes the proposed architecture, while Section 6 contains simulation results. 2. Low-Density Parity-Check Codes LDPC codes are defined as the null space of a very sparse parity check matrix H with M rows and N columns. For regular LDPC codes, H has a constant column weight of j, and a constant row weight of k. The parity check matrix is usually visualized as a bipartite graph between M check nodes and N variable nodes, as shown in Fig. 1. Every variable node of the graph corresponds to a column of H, while every check node corresponds to a row. The vari- able nodes assume binary values corresponding to the bits of the code word, while each check node is set to the modulo-2 sum of its neighbors. The code is then the set of words where all check nodes are zero. For a formal defi- nition of LDPC codes, see [1] and [2]. In this paper, we consider regular LDPC codes, where all variable nodes have a constant degree of j, and all check nodes have a constant degree of k. Moreover, we assume the codes to have a particular structure, with the top and middle part of the parity check matrix each consisting of k 2 shifted identity matrices of size L, and the bottom part of the matrix is a restricted random construction. The code structure is further described in [5]. During simulations, the column and row weights used were j = 3 and k = 6. Figure 1. Tanner graph of an example LDPC code with (N, j, k) = (10, 2, 4). v 2 v 1 v 3 v 4 v 5 v 6 v 7 v 8 v 9 v 10 c 1 c 2 c 3 c 4 c 5