Concurrent Acquisition Approach for High Resolution Sensor Arrays A versatile and compact platform to collect and display sensor data in true parallel fashion Federico Thei, Marco Bennati, Michele Rossi, Marco Crescentini, and Marco Tartagni ARCES - Advanced Research Center on Electronic Systems, Second School of Engineering, University of Bologna – Via Venezia 52, 47521 – Cesena (FC), Italy fthei@arces.unibo.it, mbennati@arces.unibo.it, mrossi@arces.unibo.it, mcrescentini@arces.unibo.it, and mtartagni@arces.unibo.it Abstract — An increasing amount of sensor applications require multiple data acquisition with high resolution in truly parallel fashion. This requirement is particularly useful in the field of Nanotechnology where concurrent acquisition is required to understand the correlation between weak stochastic events. In this paper, we will propose a sensor array readout approach where synchronous sigma-delta converters are interfacing each sensing point and whose outputs are concurrently downsampled by dedicated hardware for decimation processing. The approach shows the following advantages: on the one hand the sigma-delta conversion ensures high resolution and linearity (>12 bits), on the other, the 1-bit output allows easier routing access to the array. The approach is particularly useful in the presence of very low signals where direct raster-mode switching access to the array would compromise the signal-to-noise ratio of the readout process. As a proof of this concept, the approach is applied to an array of lipid bilayer membranes (BLMs) permitting to acquire and display single molecule event data by means of a PC-based graphical user interface (GUI). Keywords - Sensor Arrays; Nanosensors; Bilayer Lipid Membrane; Ion-channels; Delta-Sigma Converters I. INTRODUCTION Improvements in performance for high resolution sensor arrays require a new approach to elaborate large amounts of data concurrently. Moreover, device miniaturization requires a serial elaboration approach to scale the array size. Delta-Sigma converters offer high resolution and linearity on a single bit output at a high data bit rate, due to intrinsic oversampling conversion techniques, as well as low quantization noise [1]. The output of these converters need to be filtered and decimated, to achieve the noise filtering and the equivalent bit resolution in parallel format (words), ready to be used or transferred through an interface towards a PC. High throughput of data does not allow real time software elaboration, but it requires dedicated hardware processing units. Currently, field programmable gate arrays (FPGA) devices may integrate thousands of DSP slices, like the Xilinx Virtex-6 SXT (2016 slices), each containing a 25x18 bit multiplier, adder, and accumulator, running at frequency as high as 600 MHz. Thus, it appears that FPGA architecture is the most flexible to realize high throughput serial data elaboration, even for relatively large sensor arrays. A typical example of application is concurrent ion channel recording and parallel patch-clamp techniques, where the design of the electronic interface is crucial. Current sensing becomes challenging since outputs consist of signals in the pA range or even below and in the KHz bandwidth. To measure this value very low noise front-end amplifiers are needed [2][3]. Moreover, sensor array techniques, frequently used in stochastic biosensing, demand efficient strategies to address a large amount of data concurrently delivered by the system. This paper will illustrate an overview on the system architecture and the required specifics, the theory approach to the problem of the decimation and filtering, it proceeds through the FPGA implementation of the processing architecture and the Graphical User Interface (GUI) software development. The paper will end with an example of application of the implemented system. II. SYSTEM STRUCTURE The proposed system architecture is composed of three mains parts, as shown in Fig. 1: • A sensor array interfaced by Delta-Sigma (ΔΣ) converters. • An FPGA board elaborating the high rate data from the ΔΣ array. • A Graphical User Interface (GUI) on the host PC to visualize and store data transmitted through a USB link. A Delta-Sigma is an oversampling Analog-to-Digital converter (ADC) that samples the input signal at a frequency much greater than required by Shannon’s theorem and converts the information into a 1-bit stream [4]. The ratio between the input oversampling frequency @ 1MHz and the output Nyquist data rate is called oversampling ratio (OSR). Because the ΔΣ converts the input signal into a digital one, any data processing such as filtering can be performed in the digital domain. Moreover, the ΔΣ approach simplifies the routing architecture since it minimizes the number of output lines because the 1-bit data output signals and allows for the acquisition of multiple signals concurrently. To recover data at the Nyquist rate, the one bit first-order ΔΣ output data stream is filtered and down-converted by a decimator, performed by the FPGA block in parallel fashion for several channels [4]. As illustrated in Fig. 1, the FPGA processes up to twelve data streams concurrently. 2010 First International Conference on Sensor Device Technologies and Applications 978-0-7695-4094-8/10 $26.00 © 2010 IEEE DOI 10.1109/SENSORDEVICES.2010.29 88 2010 First International Conference on Sensor Device Technologies and Applications 978-0-7695-4094-8/10 $26.00 © 2010 IEEE DOI 10.1109/SENSORDEVICES.2010.24 94