International Journal of Computer Applications (0975 – 8887) International Conference on Emerging Trends in Technology and Applied Sciences (ICETTAS 2015) 1 Impact of Fin Shape on FINFET Performance Jyothi A Student College of Engineering Chengannur Alappuzha Kerala, India T E Ayoob Khan Associate Professor Electronics Department College of Engineering Chengannur Alappuzha Kerala, India Nisha Kuruvilla, PhD Electronics Department College of Engineering Chengannur Alappuzha Kerala, India Shahul Hameed T A, PhD Associate Professor Electronics Department TKM College of Engineering Kollam Kerala, India ABSTRACT FinFET has been a proven modification of the classical structure of MOSFETs to overcome short channel effect. But the leakage current due to corner effect in trigate FinFET posed impediments in its way. Fin cross section shape of FinFET has considerable impact on leakage performance. In this paper trapezium and inverse trapezium PC FinFETs with various top and bottom width of fin are studied. Results show that rounding the corner and tapering the fin reduce the leakage and improves I on /I off ratio. General Terms FinFET, Leakage Keywords PC-FinFET, Corner effect, Multithreshold 1. INTRODUCTION Miniaturization has been the watchword of the electronics industry [1] for many decades which is achieved by scaling of MOSFETs. It has contributed tremendously to the growth of semiconductor industry and in fact served as the fulcrum of its unimaginable growth in recent years. The shrinkage of the feature size of the device has led to many new challenges and such effects are consummated as short channel effects (SCE) which include V th roll-off, hot carrier effects, drain induced barrier lowering (DIBL), increase in subthreshold swing and leakage currents, etc. Hence there attained a point where industry has met with a stalemate with bulk devices as it was hardly possible to move further with Moore’s predictions. Power consumption and process variation effects were the important limiting factors of the scaling of conventional transistors beyond 22nm. The Solution to supersede these effects demand performance boosters, like use of novel materials and non-classical device structures to continue further scaling.FinFET transistors have emerged as novel devices having superior controls over short channel effects (SCE) than the conventional MOS transistor devices[2].FinFETs which provide multithreshold circuits of very low leakage without any area overhead and no requirement of additional mask. However, FinFET exhibit certain undesirable characteristics such as corner effects, quantum effects, tunneling etc. which deteriorates the performance by increasing the leakage current [3].In Trigate FinFET the premature inversion of the corners occurs due to the charge sharing effect between two adjacent gates. This causes the formation of independent channels with different threshold voltages, explained by the phenomenon cornereffect [3] [4].The mobile carrier densityin the corner of trigate FinFET is higher than the other regions and the corner regions are comparable with the planar surface channel region in small dimension devices. A larger part of the current is carried by the corners which can switch on the device. As dimensions are decreasing the effect of corner role on On-state current is increasing and the electron density distributions at the corners are higher compared to the other portion of the channel. In fact, this deteriorates the performance. Rounding the corner has been proposed as one of the ways out and FinFET with round corners is called Partially Cylindrical FinFET (PC- FinFET) [5]. For the same channel length the top fin size for desirable on and off state performance can be optimized with the change in shape of fin from round shape corner to tapered shape fin[6]. In this paper the effect of fin shape on FinFET performance is studied by rounding and tapering the fin.The different PC FinFET structures by various fin top width and various fin bottom width are simulated and compared Threshold voltage, Subthreshold swing, I off and I on /I off ratio. 2. DEVICE SIMULATION As the FinFET device structure is complex, 3D device simulation is necessary. So in this work all the FinFET device structures have been simulated using 3D device simulator. All the simulations are done without considering quantum confinement and tunneling. This analysis on the 22-nm bulk nFinFET Technology Computer Aided Design (TCAD) model with key geometries given in the Table 1. below. All other model parameters take the default value unless otherwise specified. Table 1:Key geometries of simulated structures L Gate Length 34nm H Height of the Fin 35nm W bottom Width of the Bottom of the active fin 15nm W top Width of the top of the active fin 15nm