A Leakage-Tolerant CMOS Comparator in Ultra Deep Submicron CMOS Technology Farshad Moradi 1 , Hamid Mahmoodi 2 , Hamid Alimohammadi 3 1 Department of Electrical and Computer Engineering, Ilam University, Ilam, IRAN 2 Department of Electrical and Computer Engineering, San Francisco State University, USA 3 Mahab Ghods Company, Saymareh Dam, Ilam, IRAN E-mails:{ 1 moradifarshad@gmail.com, 2 mahmoodi@sfsu.edu , 3 alimohammadi.ham@gmail.com} ABSTRACT: In this paper a new design for CMOS comparator is presented. This circuit is simulated using predictive 70nm CMOS technology models. The results show significant improvement in noise immunity and also fairly considerable total power reduction. Proposed circuit simulated for high fan-ins (8, 16, 32, and 64 bits). The results show a very small area overhead and 10% - 30% reduction in total power dissipation. Also, for some of circuits, our proposed circuit had a higher speed. INTRODUCTION High fan-in comparators are widely used in circuits, such as high-performance microprocessors, communication systems, and many other systems [7]. A faster and power efficient comparator is desirable. Superscalar microprocessors make extensive use of associative matching logic and comparators to support out-of-order execution and virtual memory mechanisms. The traditional equality comparators used for implementing associative logic in modern datapaths. in this paper, we present two comparator circuits that employed for low leakage and high speed applications. First circuit is a low power and high speed with very small area overhead. But about second circuit, is a low leakage, high speed and with no area overhead. The rest of the paper is aligned as follows: section II discusses briefly about previous work. Section III describes the proposed circuits. Section IV contains the obtained results. PREVIOUS WORKS The schematic of a high fan-in (16-input) dynamic comparator based on standard footless domino logic comparator (FLDLC) has been shown in Fig. 1. In precharge mode, all inputs go low, and the precharge node is precharged high and the output goes low. During the precharge mode, CLK is low. So, MP1 is on and MP2 is off. The precharge node started to charge to high. Then OUT node goes low and MP2 is turned on. Just when A and B are different, the pull down transistors start to discharging the precharge node. In the evaluation phase, when the clock is high, inputs are applied to the gate. If all the corresponding bits of A and B inputs are equivalent, there is no is charging path for the precharge node. However, if A and B inputs differ in any bit position, a conduction path from the precharge node to the ground is established, discharging the dynamic and causing the output to go high. In literature, some other circuits have been proposed [1], [2]. The standard Footed domino logic comparator (FDLC) has been shown in fig. 2. The N-foot transistor improves the noise immunity and reduces the total power consumption. But this circuit has an area overhead and also lower speed rather than FLDLC circuit. Fig.1 Footless Domino Logic Comparator (FLDLC) Fig.2. Footed Domino Logic Comparator (FDLC) In many situation where the circuit of Fig. 2 is used in modern datapaths (in applications alluded to earlier) mismatches occur with a much higher frequency compared to full matches. Consequently, significant energy saving can be realized if comparators and associative logic can be designed to dissipate energy only CLK Precharge Node MP1 MP2 CLK Precharge Node MP1 MP2 XXII Conference on Design of Circuits and Integrated Systems ISBN-13 978-84690-8629-2 415