 Abstract— We have conducted a critical comparison between OTCP and classical methods like SubThreshold Slop (STS), Mid- Gap (MG), Capacitance Voltage (CV), Dual-Transistor Charge- Pumping (DTCP), and Dual-Transistor Border-trap (DTBT), giving a clear insight on the benefits and limitations of OTCP. According to the experimental data, the OTCP method is often more accurate than the classical methods. On one side, OTCP offers more accurate densities of radiation-induced interface- traps (N it ) and border-trap (N bt ), while STS and MG overestimate N it because both interface- and border-trap are sensed like interface-trap. On the other side, OTCP estimates N it , N bt , and oxide-trap (N ot ) for N- and P-MOS separately, while DTCP and DTBT give average densities for whole N-MOS and P-MOS devices. Finally, N ot obtained by OTCP is in excellent agreement with that given by CV. But, they show a slight discrepancy in N it extraction. Keywords— interface-trap, oxide-trap, border-trap, extraction methods. I. INTRODUCTION he standard methods, such as CV, STS and MG [1], [2], and [3], are routinely used to qualify the radiation- induced traps in MOS devices. However, using STS and MG [2] and [3], the line between interface and border traps is hard to draw, because they are based on recording voltage-current characteristics at quasi-static or low frequency. Thus, they mistakenly recognize some border traps as interface traps [4], [5], and [6]. Regarding CV method [1], it is usually performed on a large area MOS capacitor with an oxide fabricated simultaneously with the MOSFET gate oxide in production. As a result, it requires a large area device and has also the issue of measurement extrapolation to the actual device. DTCP and DTBT methods [7] and [8] have been introduced to overcome these issues. They combine I ds -V gs and I cp -V b measurements and require both N- and P-channel transistors to be fabricated with the same technology. In addition, these methods assume that the oxide-trap density produced by irradiation is the same in both P-MOS and N-MOS transistors under similar conditions of oxide electrical field and irradiation. This assumption is not valid in all cases, because it has been shown that devices produced simultaneously by the same process on the same chip in the same production line should not automatically have the same radiation-induced oxide-trap electrical response [9] and [10]. To surmount these limitations and provide self consistency measurement, Djezzar et al. [11] and [12] have developed a new method, termed OTCP. This method is based on charge pumping [13] without a need for any additional technique and is applied on a single transistor. It separately extracts the interface, oxide, and border trap densities. It is suitable for Total Dose Radiation (TID) stress and electrical uniform stress like Fowler–Nordheim (FN). Therefore, it is very interesting to confront the OTCP method with conventional methods. The aim of this work is to make comparison between OTCP and standard methods in order to validate OTCP methodology for radiation reliability issue in MOS transistors. We show that the OTCP method is able to separate and measure the densities of all kind of traps without the need for additional electrical techniques and result extrapolation. This work is organized as follows. Set-up and experimental procedure are given in section II. An outline of the extraction methods of radiation-induced traps is presented. Analysis of the experimental results, showing the density of radiation- induced interface-, oxide-, and border-trap measured for several N- and P-MOS devices using STS, MG, DTCP, DTBT, CV and OTCP methods are presented in section III. In section IV, the OTCP method is compared to the other methods. In addition, a critical analysis, based on quantitative evaluation of N it , N ot , and N bt is presented before drawing conclusions in the last section. II. SET-UP AND EXPERIMENTAL PROCEDURE A. Device and irradiation details In this work, we investigated N-MOS, P-MOS transistors and MOS capacitors fabricated on the same chip at ISiT (Institute for Silicon Technology) of Fraunhofer, Germany. The process is a conventional (soft) dual layer metal 1 μm- CMOS twin-well technology on P-type 12 μm-epi-layer on silicon <100> substrate with 20 nm thick gate oxide layer grown in dry O 2 . The gate capacitance per unit area, C ox is about 2.12 x 10 -7 F.cm -2 . The non-packaged transistors have a gate width ranging from 10 m to 1 m with fixed gate length Oxide-Trap Charge-Pumping for Radiation Reliability Issue in MOS Devices Boualem DJEZZAR, Hakim TAHI, and Arezki MOKRANI Microelectronics and Nanotechnology Division, Centre de Développement des Technologies Avancées (CDTA), 20 Août 1956, Baba Hassen BP: 17, Algiers 16303, Algeria, phone: 213 (0) 21 35 10 40, Fax: 213 (0) 21 35 10 21, email: bdjezzar@cdta.dz . or b_djezzar@yahoo.fr . T 978-1-4244-4321-5/09/$25.00 ©2009 IEEE 287