Model Checking Based on Sequential ATPG Vamsi Boppana, Sreeranga P. Rajan, KoichiroTakayama, and Masahiro Fujita Fujitsu Laboratories of America, Inc., 595 Lawrence Expressway, Sunnyvale, CA 94086, {vboppana,sree,ktakayam,fujita}@fla.fujitsu.com Abstract. State-space explosion remains to be a significant challenge for Finite State Machine (FSM) exploration techniques in model checking and sequential verification. In this work, we study the use of sequentialATPG (Automatic Test- Pattern Generation) as a solution to overcome the problem for a useful class of temporal logic properties. We also develop techniques to exploit the existence of synchronizing sequences to reduce some temporal logic properties to simpler properties that can be efficiently checked using anATPG algorithm . We show that the method has the potential to scale up to large, industrial-strength, hardware designs for which current model checking techniques fail. 1 Introduction The state-space explosion problem that challenges Finite State Machine (FSM) explo- ration techniques such as CTL temporal logic model checking [McM93] for automa- tic formal verification has been intensively studied from various angles. There have been numerous efforts to tackle the state-space explosion problem [CGL94]. Techni- ques such as compact data structures to represent the state-space [Bry95], on-the-fly model checking [Pel96], state-space reduction techniques such as localization reduc- tion [Kur94], and navigated model checking [TSNH98] have improved the applicability of model checking towards increasingly large designs. However, past efforts in alleviating the state-space explosion problem fall short of making model checking scale up for efficient automatic verification of current, indu- strial, hardware designs. Current model checking techniques could fail in several ways including failure to extract state-transition relation information from the design structure and requiring excessive storage for functional representations of the state-space during computation. In this work, we study the use of sequential ATPG (Automatic Test-Pattern Gene- ration) algorithms [ABF90] for model checking a simple class of CTL formulae. The approach involves the construction, based on the CTL formula, of a new circuit structure from the circuit to be verified. Model checking is then cast into detecting a stuck-at- fault on the output line of the constructed circuit. The method avoids building elaborate N. Halbwachs and D. Peled (Eds.): CAV’99, LNCS 1633, pp. 418–430, 1999. c  Springer-Verlag Berlin Heidelberg 1999