International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 10 (2017) pp. 2294-2300 © Research India Publications. http://www.ripublication.com 2294 Design of Five Stage Pipelined Microprocessor with a 16K Cache Memory Aglow A George 1 , Sanjana Sadasivan 2 , Augusta Sophy* 3 School of Electronics Engineering, VIT University, Chennai, India Abstract Pipelining is a technique in which several instructions are overlapped. With this technique we can achieve a better system throughput. In this work, a five stage microprocessor is designed without interlocked pipelined stages with a 16K cache memory. MIPS (Microprocessor with Interlocked Pipeline Stages) has a 32 bit architecture with instructions of 32 bit and thirty two, 32 bit general purpose registers. Also, a cache memory is designed with a size of 16K having direct mapped configuration. The cache has four blocks, each of 4K memory size. The fundamental purpose of cache memory is to store instructions that are regularly used by the processor during the execution of program instructions. Pipelining includes subdividing the system into different stages. Each stage has buffers in between them. Here it is divided into five stages, instruction fetch stage (IF), instruction decode stage (ID), instruction execute stage (EX), memory stage (MEM) and write-back stage (WB). Each stage implements a parallelism that is executing instructions in parallel. There are cases in pipelining where subsequent instruction cannot be executed in the succeeding clock cycle. These cases or conditions are called hazards. These hazards are basically categorized into three: structural hazard, data hazard and control hazard. In this work all the above mentioned pipeline hazards are rectified. Keywords: Microprocessor; MIPS; Pipelining; MIPS Instruction Set;Cache Memory; Direct Mapped Cache Configuration; INTRODUCTION Processor is a circuitry that controls a computer and works as its central processing unit (CPU). Processor is an integral part of many electronic devices such as printers, calculators, automobiles, etc. A general processor consists of control unit, arithmetic and logic unit (ALU), memory unit and interfacing units for I/O devices. Generally processor is a circuitry that establishes memory for any electronic device. Microprocessors have two types of instruction set namely, Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC). RISC based processors have reduced number of instructions, large set of general purpose registers, instructions of fixed length and simplified addressing modes. RISC processors works on the principle of load-store architecture. Whereas CISC based processors have more number of instructions with different varieties of addressing modes and variable length instructions. RISC processors when compared to CISC processors will consume less area to implementexecute faster and have better performance making RISC processors suitable for system on chip circuitry [1]. Pipelining is a technique in which several instructions are overlapped. If pipeline is not used, first instruction will be fetched from memory and only after the execution of that instruction it goes for next instruction that is, during the instruction fetch all other units like execution units will be in idle state. Whereas if pipeline is used, when execution unit is performing its operation, it allows next instruction to be fetched. In this case no unit has to wait for the instruction, in each clock cycle each unit will get instructions continuously. The performance of a processor is measured by the access time required for the completion of an operation. Generally processors can perform much faster than a large size main memory. In order to increase the performance of main memory we can provide main memories with semiconductor memory having greater speed, but it is not economically possible. We can overcome this problem by introducing a small block called cache which is a high speed memory between processor and main memory. Instructions will be stored in both main memory and cache memory. When an instruction is to be fetched, processor will first check in the cache memory. If the instruction is not available in the cache memory it will check in the main memory [2]. The paper is arranged as follows, section II explains about MIPS processor, section III deals with the hazards in pipeline and how it is resolved, section IV defines the direct mapped cache, section V explains how the cache is implemented and section VI contains results and its discussion. MIPS PROCESSOR MIPS stand for Microprocessor without Interlocked Pipelining Stages. It was developed in 1980s by MIPS computer systems Inc. MIPS architecture is based on RISC microprocessor and is used by computer manufacturing companies like Sony, Cisco, Silicon Graphics, NEC etc. MIPS architecture contains thirty two 32 bit general purpose registers and instructions of length 32 bit. It has a built-in register ‘r0’, which always holds zero value. In the processor, for word access it uses byte addressing. MIPS have three instruction formats such as R-format, I-format and J-format. Each stage of the processor takes one clock cycle to complete the operation. It has five stages such as instruction fetch (IF), instruction decode (ID), execution (EX), memory access (MEM) and write back (WB). Program counter (PC) gives the address to instruction memory which specifies the address of the next instruction to be executed. This instruction is partitioned into separate fields as shown in table I. The op-