Multiple Chip Integration for Flat Flexible Electronics Jonathan Govaerts, Wim Christiaens, Erwin Bosman and Jan Vanfleteren Cmst – UGent / IMEC Technologiepark 914-A, B-9052 Zwijnaarde (Gent), BELGIUM jonathan.govaerts@ugent.be Abstract These days, there is a lot of interest for making electronic devices lighter and compacter, as the electronics market is rapidly expanding with all sorts of portable devices for home and everyday use. Here, a technology for embedding single thin chips in flexible substrates is further investigated so that several chips might be integrated within the same substrate. This technology offers the possibility of reducing weight, while at the same time enhancing the mechanical flexibility of the electronic circuitry. Such an integration is particularly interesting in the area of flexible displays, where the flexibility of the display is too often hampered by the rigidity of its driving electronics. Introduction Flexible substrates are often an interesting alternative for rigid PCBs because they are light and conformable. This is especially an advantage when integrating electronic devices for wearable applications. A light and flexible substrate by itself however does not guarantee a light and flexible end result. The flexibility is often drastically reduced when rigid components are assembled onto the substrate. Considering the current trend of increasing component density, which is of course welcomed for wearable devices, the benefit of the flexibility of the substrate is more and more overshadowed by the rigidity of the components. An obvious way of tackling this issue is to use smaller and thinner -and consequently also lighter components. However, when chips are thinned down to approximately 20 μm, they are too fragile to be assembled onto a substrate with standard die assembly techniques (at present). The UTCP (Ultra Thin Chip Packaging) technology, copes with this by actually embedding the ultra thin chips inside the substrate [1]. The existing UTCP technology is given in a short overview, discussing the benefits of the flat UTCP variant used here, then the design is briefly discussed, after which the fabrication and the resulting substrates are somewhat more characterized. A conclusion with a future outlook is finally presented, with a particular focus on the area of flexible displays, where flatness of the substrate is crucial for further processing of display backplanes. Technology Flow The technology used here is an enhanced version of IMEC’s first UTCP (Ultra Thin-Chip Packaging) technology with an updated process flow to realize a more symmetrical package. The used process flow is depicted in Figure 1. Figure 1 The base PI layer is spincoated onto a rigid (glass) carrier substrate and cured. Then the photodefinable PI is spincoated, illuminated through a mask and developed to define the chip cavity. After curing, the chip is placed face up, using BCB in the cavity as adhesive. The BCB is cured, and the top layer of PI is spincoated and cured in the same way as the base PI layer (thus creating a symmetrical substrate sandwich). The via holes to the chip contacts are laser drilled and after the metal pattern is realized on top, the substrate can be released from its carrier. Test Design The chips used for the embedding trials are thinned- down test chips available at IMEC. They are specified as PTCK chips, which stands for “Packaging Test Chip version K”, and measure 5 mm by 5 mm. There are four different versions of PTCKs, but all have the same peripheral bond pad layout, which is all that will be used in the tests described in this paper. This bond pad layout, and how they are connected, is shown in Figure 2. The bond pads at the periphery come in 3 pitches, 100, 60 and 40 μm, and a more zoomed view on the right shows the different interconnection schemes on the chip.