IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 5, MAY 2013 737 Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis Yu-Hsiang Lin, Shi-Yu Huang, Senior Member, IEEE, Kun-Han Tsai, Senior Member, IEEE, Wu-Tung Cheng, Fellow, IEEE, Stephen Sunter, Senior Member, IEEE, Yung-Fa Chou, Member, IEEE, and Ding-Ming Kwai, Member, IEEE Abstract —A parametric delay fault could arise in a through- silicon via (TSV) of a 3-D IC due to a manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield- learning, and/or reliability screening. In this paper, we present an innovative design-for-testability technique called variable output thresholding. We discovered that by dynamically switching the output of a TSV from a normal inverter to a Schmitt–Trigger inverter, the parametric delay fault on the TSV can be character- ized and detected. SPICE simulation reveals that this technique remains effective even when there is significant process variation. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32 768 TSVs when the test clock is running at 10 MHz. Index Terms—3-D IC, design for testability, parametric delay fault testing, through-silicon via, through-silicon vias (TSV) testing. I. Introduction A 3-D IC might use many through-silicon vias (TSVs) to connect several dies, and it could malfunction if one of the TSVs is defective. It might comprise dies and connections fabricated by different parties (e.g., logic wafer foundries, DRAM makers, and assembly houses). A standardized test interface that is able to shed light on the performance of each manufactured TSV is desirable because it can serve as a common platform to resolve any potential dispute on the responsibility of failing parts, and to assist the silicon debugging, failure analysis, and yield ramp-up. Manuscript received June 11, 2012; revised October 14, 2012; accepted December 7, 2012. Date of current version April 17, 2013. This work was supported in part by the National Science Council (NSC) of Taiwan under Grant NSC-101-2220-E-007-015 and Industrial Technology Research Institute, HsinChu, Taiwan. This paper was recommended by Associate Editor K. Chakrabarty. Y.-H. Lin was with Department of Electrical Engineering, National Tsing Hua University, HsinChu 30013, Taiwan (e-mail: yhlin2@larc.ee.nthu.edu.tw). S.-Y. Huang is with Department of Electrical Engineering, National Tsing Hua University, HsinChu 30013, Taiwan (e-mail: syhuang@ee.nthu.edu.tw). K.-H. (Hans) Tsai, W.-T. Cheng, and S. Sunter are with Silicon Test Solutions Division, Mentor Graphics Corporation, Wilsonville, OR 97070 USA (e-mail: hans − tsai@mentor.com; wu-tung − cheng@mentor.com; Stephen − Sunter@mentor.com). Y.-F. Chou and D.-M. Kwai are with Information and Communications Labs, Industrial Technology Research Institute, HsinChu 31040, Taiwan (e-mail: yfchou@itri.org.tw; dmkwai@itri.org.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAD.2012.2236837 Delays across TSVs are less predictable in a 3-D IC than 2-D interconnects (due to potential mechanical stresses during wafer thinning and die stacking). As reported in [4] and [15], 3-D ICs could suffer from nonnegligible yield loss due to the malfunctioning of the TSVs. From a performance point of view, it is essential to predict the actual delay across every TSV in a 3-D IC, in the mass-production stage for small delay testing and during fault diagnosis or silicon debugging for yield learning. In general, a TSV is a wide interconnecting wire, with very small resistance but large capacitance. An in-depth investiga- tion of the interconnect delay model can be found in [16]. A design for direct delay measurement was proposed in [17], in which the oscillation ring concept was applied to characterize the delay of a cell in a closed-loop manner. Throughout this paper, we use RO to denote a ring oscillator. An RO consists of a logical ring structure with an odd number of inversions. It oscillates autonomously with a period equal to twice the propagation delay around the ring. In [6], the RO is further utilized to characterize the capacitance of a transmission line. In [1] and [5], a cell delay inside an RO can be obtained by postmeasurement mathematical analysis. Furthermore, the RO can be utilized to test stuck-at faults and delay faults associated with the interconnect wires in a 2-D IC, as demonstrated in [13], [14], and [18]. These schemes, though effective, may not be readily applicable to the TSVs in a 3-D IC. On the one hand, postbond TSVs can be tested by a system- level scan test supported by a 3-D IC test infrastructure [8], [10], [12], [15]. On the other hand, one can also perform test on the TSVs through dedicated TSV built-in self-test structure [7]. These methods are effective for the detection of a catas- trophic fault in a TSV (such as a stuck-at fault or a completely open fault). However, they may not be adequate for the char- acterization, diagnosis, and yield learning of parametric delay faults. Very recently, a method was proposed in [20] to detect parametric delay faults. It incorporates a transistor connected at each TSV to form a voltage divider with the faulty resistance of the TSV, and uses an analog comparator to detect the re- sulting voltage to perform a pass/fail test. The method requires an analog reference voltage distributed to all TSVs under test. The oscillation ring concept with a so-called input sensi- tivity analysis technique was proposed in [19] (which will 0278-0070/$31.00 c  2013 IEEE