Technical Report Material selection methodology for gate dielectric material in metal–oxide–semiconductor devices B.N. Aditya, Navneet Gupta ⇑ Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani, Rajasthan, India article info Article history: Received 8 September 2011 Accepted 11 October 2011 Available online 25 October 2011 abstract Due to the continuous scaling of metal–oxide–semiconductor (MOS) devices, SiO 2 can no longer be used as a gate dielectric, so it has to be replaced by some suitable high-j dielectrics. As there are variety of high-j dielectrics available to designer, so there is a need for a proper technique to select the best pos- sible material. In this paper, we present a materials selection based on the Ashby’s methodology to opti- mise the choice of gate dielectric material in MOS devices. In this work, performance indices and material indices have been developed for gate material in MOS devices and thereafter material selection chart is plotted. The selection chart shows that La 2 O 3 is the most suitable materials followed by HfO 2 and ZrO 2 for being used as gate dielectric in MOS devices. Ó 2011 Elsevier Ltd. All rights reserved. 1. Introduction With the rapid advancement in semiconductor technology, the silicon industry has been scaling silicon dioxide (SiO 2 ) aggressively for low-power, high-performance applications in metal oxide semiconductor (MOS) devices. The number of transistors on a chip has been increasing exponentially in accordance with Moore’s Law [1]. The scaling of the MOS devices has become the driving force for the semiconductor industry to achieve the versatile functionality and better performance of the integrated circuit at a low cost [2,3]. For decades, silicon dioxide (SiO 2 ) has been showing excellent performance as a gate dielectric due to its high resistivity, large band gap and large conduction band offset, high melting and crys- tallization temperature and high quality Si/SiO 2 interface. As the International Technology Roadmap for Semiconductors (ITRSs) [4] is anticipating 35 nm design rules by 2014, so it will be difficult to continue SiO 2 as a gate material in MOS devices. Because as gate oxides are made thinner, the tunneling barrier in the gate oxide be- comes so thin that the electrons in the conduction band of Si un- dergo direct tunneling i.e., they tunnel through the gate oxide and emerge in the gate, without having to go via the conduction band of the gate oxide. Due to this tunneling, high input impedance for MOS devices is degraded, which is not desirable. However, in order to increase the drain current in MOS devices, it is necessary to increase the gate capacitance, which is inversely proportional to gate oxide thickness. So the only possibility to have high value of gate capacitance is to use insulators having dielectric constant higher than SiO 2 . In doing so, the tunneling barrier remains wide and the gate oxide field will become low, thereby keeping the gate tunneling leakage current low. Such high dielectric constant insu- lators are known as high-j gate dielectrics. A systematic consider- ation of the required properties of gate dielectrics has yielded some key criteria for selecting an alternative gate dielectric [5]. Some of the dielectric materials that are being investigated as replacement for SiO 2 are Al 2 O 3 , ZrO 2 , La 2 O 3 Ta 2 O 5 , TiO 2 , HfO 2 , ZrSi x O y ,Y 2 O 3 , Ya 2 O 3 [6]. However, all these materials have some practical limita- tions due to mobility degradation and phonon scattering. Hence it is imperative to optimize device performance by suitable selection of dielectric gate material. Also it is assumed that in case of using ultrathin high-j dielectrics, these films are fabricated using a low temperature growth technique to sustain the amorphous structure. An effective method of material selection is the Ashby approach proposed by Ashby [7]. For microscale designs the Ashby approach is widely accepted [8–11]. This approach is extended in this paper for the selection of high-j dielectric gate materials in MOS devices. The key performance indices for dielectric materials are identified and these competing factors are compared for various materials. This paper examines the various criteria and analyses each mate- rial with respect to these requirements. This paper is organized as follows: Section 2 describes the desir- able criteria for high-j dielectric gate material. Section 3 describes the Ashby approach and it is application in this study. Section 4 explains the results and discussion and finally Section 5 gives the conclusion of the proposed study. 2. Desirable criteria of high-j dielectric gate material The following properties are to be considered while choosing an alternate gate dielectric to replace SiO 2 in MOS devices. 0261-3069/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.matdes.2011.10.015 ⇑ Corresponding author. Tel.: +91 1596515411. E-mail addresses: bn.aditya.1@gmail.com (B.N. Aditya), ngupta@bits-pilani.ac.in (N. Gupta). Materials and Design 35 (2012) 696–700 Contents lists available at SciVerse ScienceDirect Materials and Design journal homepage: www.elsevier.com/locate/matdes