27 0740-7475/02/$17.00 © 2002 IEEE September–October 2002 The impact of noise and coupling mecha- nisms on IC performance is different from that related to traditional failure mechanisms on which test technology efforts have recently focused. Testing techniques for noise will extend the domain of conventional test approaches to mixed parametric and functional test strategies. The dI/dt and dV/dt noise generation (switching noise) and propagation mechanisms address this larger domain of test approaches. Simultaneous switching noise Simultaneous switching of multiple digital gates demands large transient-current spikes. These spikes cause simultaneous switching noise (SSN), also known as dI/dt noise, power supply noise, or ground/power bounce. The package V DD pin introduces series resistance R VDD and induc- tance L VDD in the path from the external power supply to the on-chip power supply. For a single gate, the transient voltage at the power supply due to resistive and inductive effects is given by V DD_on-chip = V DD – R VDD I DD – L VDD (dI DD /dt) The second term in the expression is a tran- sient IR drop on the on-chip V DD , and the third term is the dI/dt noise; transient current pulse I DD causes both. The return path of I DD passes through the V SS package pin, closing the loop and generating a positive spike at the on-chip V SS node due to V SS pin inductance and resis- tance, as Figure 1 (next page) shows. The over- all effect of the switching current is a transient reduction of the on-chip power supply voltage (V DD_on-chip –V SS_on-chip ) due to both the IR drop and dI/dt noise. The current’s time derivative, for well-sized logic gates, is proportional to the input rise or fall time and the transistors’ maxi- mum saturation current. When multiple gates switch simultaneously, the individual switching currents combine to increase the amount of SSN. The reason output driver gates switch simultaneously is that all of an output bus’ nodes should switch at once. For core logic cells, the different propagation paths found have a Gaussian path delay distribution. Noise Generation and Coupling Mechanisms in Deep-Submicron ICs On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques depends on the circuit, its implementation, and the possible physical failures and parasitic coupling models. This new demand for test technology practices precipitated the investigation of dI/dt and dV/dt noise generation and propagation mechanisms. Xavier Aragonès, Jose Luis González, Francesc Moll, and Antonio Rubio Universitat Politècnica de Catalunya Authorized licensed use limited to: UNIVERSITAT POLITÈCNICA DE CATALUNYA. Downloaded on December 9, 2009 at 02:23 from IEEE Xplore. Restrictions apply.