196 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART A, VOL. 20, NO. 2, JUNE 1997 Voltage Variant Source Side Injection for Multilevel Charge Storage in Flash EEPROM Donato Montanari, Jan Van Houdt, Dirk Wellekens, Guido Vanhorebeek, Luc Haspeslagh, Ludo Deferm, Guido Groeseneken, Senior Member, IEEE, and Herman E. Maes, Senior Member, IEEE Abstract—The growing demand for high-density Flash memo- ries in portable computing, smart cards, and telecommunications applications has boosted the efforts on Flash memory cell size scaling and cost reduction [1]. In order to further increase the storage capability and, consequently, reduce the cost per bit of Flash memories, multilevel charge storage (MLCS) techniques have recently gained a lot of interest [1], [2]. Furthermore, MLCS is considered a viable route for increasing embedded Flash density as well. The devices investigated so far, rely either on conventional channel hot electron (CHE) injection or on Fowler–Nordheim tunneling (FNT) for programming [3]. For the first time, this paper shows that source side injec- tion (SSI) is also an excellent candidate for MLCS. The main advantages of SSI for MLCS are the very narrow threshold- voltage distributions after SSI programming, the symmetrical threshold-voltage window and the overerase immunity, which allows an overall wider threshold-voltage window, and hence more separated distributions. Index Terms— Euclidean distance, multilevel flash memories, parallel sensing, read out architecture, source side injection. I. INTRODUCTION I N ORDER for Flash technology to access the profitable market of mass storage for portable applications, the cost per bit must be reduced. Up to now, the much higher cost of Flash memory as compared to magnetic storage devices has compromised many of the advantages of this particular technology such as, for instance, increased reliability, lower power consumption and improved portability. Device scaling techniques are expected to take cost down to $1/Mbyte by the year 2000 [2]. Provided that no extensive additional circuitry is needed to write and read multiple charge levels, multilevel charge storage (MLCS) would further reduce this cost by at least a factor of two. In fact, the memory density would double without a die size increase if four different levels could be stored in a single cell and the corresponding currents could be read out. The programming schemes investigated so far are based on Fowler–Nordheim tunneling (FNT) or channel hot elec- tron (CHE) injection and utilize a bit-by-bit program verify procedure that results in a trade-off between the accuracy of the levels and the programming speed and, consequently, slows down the programming operation, significantly lowering the data throughput of the MLCS memory. Moreover, the Manuscript received January 17, 1997; revised March 3, 1997. This work was presented in part at the 6th Nonvolatile Memory Technology Conference, Albuquerque, NM, 1996. This work was supported by Siemens AG. The authors are with IMEC, Leuven B 3001, Belgium. Publisher Item Identifier S 1070-9886(97)03863-8. Fig. 1. SSI device structure and layout. chip implementation of the verify scheme increases the die size. Obviously, a reliable, fast and nonverified multilevel programming method would be very interesting especially for embedded applications where the relative area cost of the verify scheme would be much higher than in stand-alone applications. In this paper, a new programming scheme for MLCS is proposed: voltage variant source side injection (VVSSI) [4]. The scheme is based on source side injection (SSI), it utilizes a single 1 s programming pulse and does not require a verify scheme. In Section I, the programming performance and ca- pability for information discrimination are explained in detail. In Section II, endurance characteristics are reported. Finally, in Section III, a new read out architecture is introduced which is specifically designed to identify the levels of a cell when programmed without a verify scheme. II. MULTILEVEL PROGRAMMING MECHANISM SSI has recently qualified as an alternative programming mechanism for binary Flash Memories since it combines high injection efficiency with low power consumption, its driving force being the extremely high programming speed [5]. The structure of the utilized memory device, which has been realized in a 0.7- m embedded Flash technology, is shown in Fig. 1 [5]. The device is based on a complementary metal- oxide-semiconductor (CMOS)-compatible split-gate structure 1070–9886/97$10.00  1997 IEEE