ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia Design and Simulation of a High Performance Lateral BJTs on TFSOI Ismail Saad and Razali Ismail Faculty of Electrical Engineering, University Technology Malaysia, 813 10, Skudai, Johor Bharu, E-mail: Abstract Lateral BJT's have received renewed interest with the advent of BiCMOS and Silicon on Insulator (SOI) technology. It's been reported in [1] that a 67 GHz fmax novel lateral BJT's on TFSOI has been fabricated with a simplified process. This paper presents an investigation of this high performance transistor by using 2D process and device numerical simulation. Accurate geometrical structure and reasonably good doping profiles with a simple fabrication process are successfully achieved in the process simulation. However, a careful attention is required to define the mesh for the device to obtain an accurate measurement of device characteristics. With a base, low-doped collector, emitter and high-doped collector concentrations of 3 x 1017 cm 3, 1.0 x 1017 cm3, 5 x 1020 cm-3 and 3 x 1020 cm-3 respectively, a variation of 0.1- 0.13pim base width is observed. I-V and frequency performance of these transistors are simulated and analyzed. Y-parameter measurement at frequency 10 MHz - 1000 GHz shows a 21 GHz fmax was successfully achieved at VBE=0.7V, VCE=2.OV and ICE=6.O ,uA. I. INTRODUCTION Most existing BiCMOS processes combine high- performance vertical BJT's with MOSFET's. These technologies offer a trade-off between speed and power dissipation and attain digital/analog systems with a performance exceeding that of circuits based on either technology alone [2, 3]. This results in a rather complex and expensive process due to the technological incompatibility of two types of transistors [4]. Several sophisticated technologies such as self-aligned double-polysilicon structure [5], shallow and/or deep trench isolation [6] and an epitaxial base [7] has been used. However, such superior process technologies increase fabrication costs of RF LSI's. Consequently, the cost of the extra steps to produce the buried layer and epitaxial collector vertical bipolar transistors has also limited BiCMOS LSI's marketability [8]. With the advantages of low power and high speed operation and simpler integration of devices, Silicon on Insulator (SOI) has become an excellent candidate as an alternative substrate for BiCMOS circuits. Furthermore, the use of SOI as a substrate in BiCMOS circuits is dependent on the development of a proper bipolar device (in a lateral structure) on SOI [9]. A number of novel high performance lateral bipolar's on SOI have been proposed and implemented. All of these transistors have been fabricated with a different approach of structure. This paper presents an investigation of a high performance transistor by carrying 2D process and device numerical simulation [10]. With a base, low-doped collector, emitter and high- doped collector concentrations of 3 x 1017 cm-3, 1.0 X 1017 cm-3 5 x 1020 cm-3 and 3 x 1020 cm-3 respectively, a variation of 0.1- 0.13ptm base width is observed. I-V and Frequency performance of these transistors are simulated and analyzed. Y-parameter measurement at frequency 10 MHz - 1000 GHz shows a 21 GHz fmax was successfully achieved at VBE=0.7V, VCE=2.OV andICE=6 .0 ptA. II. DEVICE STRUCTURE AND PROCESS Figure 1 shows the schematic structure of the lateral bipolar transistor considered in the present study. Fig. 1 Schematic 3D cross-sectional view of lateral BJT The intrinsic base is formed by an angled (45°) boron and BF2 ion implantation with the condition of BF2 1.2x1 012 cm-2 at 25KeV, boron 0-7803-9731-2/06/$20.00 ©2006 IEEE 554 Authorized licensed use limited to: UNIVERSITY TEKNOLOGI MALAYSIA. Downloaded on January 6, 2009 at 19:18 from IEEE Xplore. Restrictions apply.