Field-effect control of breakdown paths in HfO 2 based MIM structures X. Saura a,⇑ , X. Lian a , D. Jiménez a , E. Miranda a , X. Borrisé b,c , F. Campabadal b , J. Suñé a a Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Spain b Institut de Microelectrònica de Barcelona (IMB-CNM), CSIC, Bellaterra, Spain c Institut Català de Nanotecnologia, Bellaterra, Spain article info Article history: Received 24 May 2013 Received in revised form 3 July 2013 Accepted 16 July 2013 abstract The field-effect control of the conduction through dielectric breakdown paths is explored in lateral W/ HfO 2 /W nanogap structures. The lateral size of the conducting filament is controlled by changing the cur- rent compliance during the voltage-ramp stress used to induce the breakdown. Partial destruction of the breakdown path is also shown to be possible by using a partial reset methodology. The results suggest that field-effect control of the breakdown path conduction is feasible. However, the capacitive coupling of the gate to the conducting filament is much smaller than that of drain and source due to unavoidable constraints associated with the considered test structures. As a consequence, extreme short channel effects limit the gate control of the filament conduction as demonstrated by simulations based on the top-of-the-barrier electrostatic model for nanowire transistors. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction Voltage-controlled anti-fuse devices based on breakdown (BD) paths might be useful to implement reconfigurable computing architectures. On the other hand, metal–insulator–metal (MIM) structures are of interest for nonvolatile Resistive Random Access Memories (RRAM) because of its resistive switching (RS) proper- ties. The principle of operation of these devices is the creation and disruption of a conduction filament (CF) similar (if not identi- cal) to a soft BD path [1]. Application of appropriate electrical sig- nals enables the switching of the CF between a high resistive state (HRS) and a low resistive state (LRS). These RS devices are identi- fied with memristors and are expected to have a great impact for non-volatile memory and reconfigurable logic applications. The use of three terminal gate-controlled memristive devices might also be interesting due to its increased functionality. To enable these three terminal devices the gate voltage control of the con- duction and switching properties of the CF becomes essential. In this work, we assess the feasibility of using BD paths to implement voltage-controlled anti-fuse devices. Our basic assump- tion is that a BD path behaves as a nanowire and that the conduc- tion of this nanowire can be controlled by field effect when it is capacitively coupled to a metal gate. Recently, experimental results concerning the post-BD conduction through soft and hard BD paths in thin SiO 2 -based and high-K gate dielectrics were shown to be well understood within a quantum point contact (QPC) model, thus supporting our basic assumption of nanowire conduction through BD paths [2–4]. Although nanowire field-effect transistors have already re- ceived much attention in the literature, the field-effect control of the conduction through BD paths still needs to be experimentally demonstrated. To explore this issue, we fabricated three terminal devices con- sisting of a (broken down or electroformed) lateral W–HfO 2 –W nanogap structure with a metal back-gate. With these test struc- tures we have obtained preliminary results which indeed suggest the feasibility of field-effect control of the CF conduction. 2. Sample fabrication A scanning electron microscope (SEM) image and schematic cross-sections A-A 0 and B-B 0 of the structure under study are shown in Fig. 1. The device is a transistor-like structure consisting of two metal source/drain (S/D) electrodes, with a separation of few nano- meters, deposited on top of a HfO 2 layer grown onto a W layer that is expected to behave as a back-gate electrode (G). The structure is fabricated by a combination of conventional optical lithography and electron beam lithography (EBL) to define the critical nanogap region. Fig. 2 shows a SEM image of the critical nanogap region of one of the devices. In this particular case, the separation between the metal electrodes was approximately 8.9 nm. The fabrication process was initiated by the sputtering of the W back-gate layer. After this, the HfO 2 layer was deposited by ALD and the M2 and M3 layers were deposited by sputtering and lift-off processes. After device fabrication, the CF was created by applying electrical stress between the metal electrodes. Usually, this electroforming process 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.07.061 ⇑ Corresponding author. Address: Universitat Autònoma de Barcelona, Departa- ment d’Enginyeria Electrònica, Cerdanyola del Vallès, 08193 Barcelona, Spain. Tel.: +34 935813521. E-mail address: xavier.saura.mas@uab.cat (X. Saura). Microelectronics Reliability 53 (2013) 1346–1350 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel