Please cite this article in press as: Chong W-K, et al. Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application. Int J Electron Commun (AEÜ) (2013), http://dx.doi.org/10.1016/j.aeue.2013.07.009 ARTICLE IN PRESS G Model AEUE 51076 1–5 Int. J. Electron. Commun. (AEÜ) xxx (2013) xxx–xxx Contents lists available at ScienceDirect International Journal of Electronics and Communications (AEÜ) jo ur nal ho me page: www.elsevier.com/locate/aeue Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application Wei-Keat Chong a , Harikrishnan Ramiah a,∗ , Gim-Heng Tan b , Nandini Vitee a , Q1 Jeevan Kanesan a a Department of Electrical Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia b Department of Electrical and Electronic Engineering, University Putra Malaysia, 43400 Serdang, Malaysia a r t i c l e i n f o Article history: Received 9 May 2013 Accepted 19 July 2013 Keywords: LNA Mixer Ultra-low voltage Ultra-low power CMOS ZigBee a b s t r a c t This work describes the design and implementation of an ultra-low voltage, ultra-low power fully differ- ential low noise amplifier (LNA) integrated with a down-conversion mixer for 2.4 GHz ZigBee application. An inductive-degenerated cascoded LNA is adapted and integrated with a double-balanced mixer which is targeted for low-power application. The proposed design has been extracted and simulated in a 0.13 m standard CMOS technology. With a power consumption of 905 W at a voltage headroom of 0.5 V, the proposed LNA-mixer integration reaches out to an integrated noise figure (NF) of 7.2 dB, a gain of 22.3 dB, 1 dB compression point (P1 dB) of -22.3 dBm and input-referred third-order intercept point (IIP3) of -10.8 dBm. © 2013 Published by Elsevier GmbH. 1. Introduction The development of low power transceiver is driven by the need of prolonging battery life time in the implementation of wire- less systems catering towards mobile application. The simplicity in protocol, along with high density of nodes, has prompted IEEE 802.15.4, ZigBee as a preferred wireless personal area network (LR- WPAN) standard targeted towards low cost, low power and low data rate implementation [1]. With a regulated operating band- width of ZigBee from 2.4 GHz to 2.4835 GHz, supporting a data rate 250 kbps, coupled with a sensitivity requirement of -85 dBm [2], the standard fit well into the applications such as medical devices in personnel health care sector, home automation, con- sumer electronic devices and video games, highlighting minimal power dissipation requirement [3]. The conventional architecture of receiver generally integrates discrete, independent low noise amplifier (LNA), mixer and voltage control oscillator (VCO) coupled together with inter-stage match- ing network, balun or filters. These interleaving circuits lead to additional power consumption and unwanted parasitic compo- nents due to the increased complexity of the system. ∗ Corresponding author. Tel.: +60 37967 5262; fax: +60 37967 5316. Q2 E-mail address: hrkhari@um.edu.my (H. Ramiah). The continuous downscaling of channel length in deep- submicron CMOS technology in proportion to the voltage headroom limitation up to 1.2 V and below, outlays design chal- lenges in the construction of RF front-end block [4]. This has driven the need in the exploration of new design technique for current RF architecture. As an aftermath of voltage headroom limitation, series stacking is alleviated. Often folded cascode topology is preferred as it sits well into the implementation of low-voltage headroom real- ization. Addressing the need in reduced power consumption, active chip area and production cost, the lossy and bulky integration of power hungry buffers, balun and inter-stage matching networks to the main blocks is discarded through single chip integration of LNA-mixer at the front-end receiver. As a bench of comparison, recent reported works of low power LNA-mixer implementation still observe high voltage headroom and power consumption [5–7]. This work reports the design and analysis of ultra-low voltage, ultra-low power fully differential integrated LNA-mixer in com- pliance to IEEE 802.15.4 regulation. The integrated architecture is extracted, simulated and verified on a 0.13 m standard CMOS plat- form. The preference towards a differential architecture is derived upon the ability in rejecting common-mode noise [8]. This feature sets a perquisite of symmetrical physical realization, thus improv- ing the noise figure of the architecture deemed to be critical in low noise amplifier design. The differential realization also improves the linearity performance of the mixer due to even order nonlin- earity cancellation. This paper is organized as follows. Section 2 1434-8411/$ – see front matter © 2013 Published by Elsevier GmbH. http://dx.doi.org/10.1016/j.aeue.2013.07.009 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66