DYNAMICALLY RECONFIGURABLE DCT ARCHITECTURES BASED ON BITRATE, POWER, AND IMAGE QUALITY CONSIDERATIONS Yuebing Jiang and Marios Pattichis University of NewMexico Department of Electrical and Computer Engineering Albuquerque, NM 87106 {yuebing, pattichis}@ece.unm.edu ABSTRACT We propose a dynamically reconfigurable DCT architecture system that can be used to optimize performance objectives while meeting real-time constraints on power, image qual- ity, and bitrate. The proposed system can be dynamically re- configured between 4 different modes: (i) minimum power mode, (ii) minimum bitrate mode, (iii) maximum image qual- ity mode, and (iv) typical mode. The proposed system relies on the use of efficient DCT implementations that are parameterized by the word-length of the DCT transform coefficients and the use of different quan- tization quality factors. Optimal DCT architectures and qual- ity factors are pre-computed on a training dataset. The pro- posed system is validated on the LIVE database using leave- one-out. From the results, it is clear that real-time constraints can be successfully met for the majority of the test images while optimizing for the 4 modes of operation. Index Terms— DCT, finite word length, quantization, Dynamic Partial Reconfiguration. 1. INTRODUCTION Modern mobile devices require image processing solutions that can scale with available power. Wireless networks im- pose specific constraints on available bandwidth, while users are interested in the quality of the transmitted images. Taken together, we thus have opposing constraints on power, bitrate, and image quality. The design of image compression hard- ware usually attempts to provide a static hardware solution that can balance these constraints. Unfortunately, the con- straints can change in real-time. For example, there is a need for a low-power solution when the battery level of a mobile device is significantly depleted. Network requirements can vary based on location. Furthermore, requirements on image quality can vary based on the changing interests of the user. We propose the development of a dynamically reconfigurable framework that allows the hardware to adapt to these require- ments. For addressing some of these issues, we focus on the development of a dynamically-reconfigurable system for the DCT. Thus, our proposed system will be compatible with image and video compression standards that rely on the DCT. In fact, we will demonstrate our system as a part of baseline JPEG. In terms of practical usage, we introduce new DCT hardware configurations that reflect realistic scenarios for image compression. These scenarios include: (i) minimum power mode, (ii) minimum bitrate mode, (iii) max image quality mode, and (iv) typical mode. All modes are subject to constraints based on the maximum available power, minimum acceptable image quality, and maximum bitrate. We refer to the methods section for details. The proposed system can dynamically reconfigurable the hardware from one of these modes to another. Furthermore, by changing the constraints, it is clear that we can generate different hardware solutions. The use of dynamic partial reconfiguration with 2D DCT architectures has also been considered in [4, 5]. In [5], the au- thors use dynamic partial reconfiguration to modify the DCT architectures based on an estimate of the number of DCT co- efficients that will be zero. In [2], the authors considered the effect of varying the number of bits used for representing the data path. Compared to prior work in this area, this paper in- troduces a new, multi-objective optimization framework for evaluating DCT architectures in terms of image quality, dy- namic power, and bitrate, and training and validation of the method using the LIVE Image Quality database [3]. The rest of the papers is organized as follows. The methodology is given in section 2. Implementation results are given in 3. Concluding remarks are given in section 4. 2. METHODOLOGY A block diagram of the proposed system is shown in Fig 2. Real-time constraints and selected mode of operation are in- put to the dynamic reconfiguration (DR) controller. The pre- computed Pareto-optimal DCT architectures and correspond- ing Quality factor are selected by the DR controller. The