Materials Science and Engineering B 154–155 (2008) 49–55 Contents lists available at ScienceDirect Materials Science and Engineering B journal homepage: www.elsevier.com/locate/mseb Defect engineering aspects of advanced Ge process modules C. Claeys a,b,∗ , E. Simoen a , K. Opsomer a,b , D.P. Brunco c , M. Meuris a a IMEC, Kapeldreef 75, B-3001 Leuven, Belgium b E.E. Department, KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium c IMEC, Industrial Resident from Intel, Santa Clara, USA article info Article history: Received 17 June 2008 Accepted 28 July 2008 Keywords: Ge processing Shallow junctions Implantation damage Germanidation abstract Germanium receives world-wide a renewed interest due to its strong potential as high-mobility chan- nel material for deep submicron high-performance technologies. Ge processing has been demonstrated to be compatible with Si technology and has the important benefit that compared to Si lower thermal budgets are required for dopant activation and implantation-induced defect anneal. However, many chal- lenges remain, like interface passivation, gate stack formation, contact technology, and the fabrication of high-performing n-channel devices. This review will cover some advanced Ge processing modules from a viewpoint of defect control and engineering. Attention is first briefly given to defect aspects related to the fabrication of bulk Ge substrates or thin Ge films on either oxide or Si. Next shallow junction formation is addressed, where the thermal anneal procedure must be optimised for minimising junction depth with- out compromising dopant activation and defect annealing. The discussion will focus on different dopant species such as B, P, As and Sb. Finally, the contact technology is addressed for a variety of germanides, i.e., Co, Cu, Ni, Fe, Pd, Pt, etc. A control of the metal interaction with point defects and geometrical effects play a crucial role for performance optimisation and yield enhancement. © 2008 Elsevier B.V. All rights reserved. 1. Introduction The downscaling of CMOS technologies requires the intro- duction of advanced processing modules, such as high- gate dielectrics, ultra-shallow junctions, metal gates, alternative device architectures, etc. in order to meet the stringent performance specifications of the ITRS roadmap [1]. As these process mod- ules may lead to a reduction of the carrier mobility, 45 nm and below process flows are commonly based on the implementation of strain-engineering using either a global or local approach [2]. The process-induced stressors enable on the same wafer tensile stress for the n-channel and compressive stress for the p-channel devices. An alternative approach is to start with a substrate mate- rial with higher carrier mobilities than in silicon as is the case for germanium, exhibiting a three times higher electron and four times higher hole mobility. Being the semiconductor material at the basis of the invention of the solid-state devices and the integrated circuit, bulk Ge was in the 1960s replaced by silicon to overcome process- ing difficulties associated with the planar technology requiring the thermal growth of stable high-quality oxides and good surface pas- ∗ Corresponding author at: IMEC, Kapeldreef 75, B-3001 Leuven, Belgium. Tel.: +32 16 281328; fax: +32 16 281214. E-mail address: claeys@imec.be (C. Claeys). sivation [3]. However, the research quest in the 1990s for high- dielectrics to replace SiO 2 , leading to the switch over from ther- mal oxidation to advanced deposition techniques (CVD, MOCVD, ALD, epitaxial growth) also triggered a renewed interest in Ge for microelectronics applications. For a historical overview of the use of germanium reference is made to the review of Haller [5], while a recent book is covering the present status of Ge-based technologies from materials to devices [6]. Today, a good electrical performance is achieved for short-channel p-MOSFETs with hole mobilities above 350 cm 2 /V s, while the n-MOSFETs performance is hampered by poor interface quality and difficulties in controlling the behavior of the n-type dopants [7,8]. The latter will be further elaborated. Although Ge processing can essentially be done in a Si process line, the different process modules have to be fine-tuned to take into account some peculiarities associated with the Ge technology and requiring alternative approaches for wafer cleaning, surface pas- sivation, shallow junction formation and contact technology. The aim of the present review is to focus on some key aspects of defect formation and control. The defect engineering will be illustrated with examples related to substrate fabrication, shallow junction formation and germanidation. The structural and electrical defect analyses include transmission electron microscopy (TEM), X-ray diffraction (XRD), scanning electron microscopy (SEM), deep-level transient spectroscopy (DLTS), I–V and C–V characteristics, and low frequency noise studies. 0921-5107/$ – see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2008.07.004