Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis Chang-Chih Chen, Fahad Ahmed, Linda Milor ⇑ School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA article info Article history: Received 22 May 2013 Accepted 7 June 2013 Available online xxxx abstract A framework is proposed to analyze the impact of negative bias temperature instability (NBTI) and posi- tive bias temperature instability (PBTI) on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory, embedded within a system running a variety of standard benchmarks. We study DC noise margins in con- ventional 6T SRAM cells as a function of NBTI/PBTI degradation and provide insights on memory reliabil- ity under realistic use conditions. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction Increasing operating temperatures and electrical fields, com- bined with the scaling of dimensions, have contributed to faster aging due to NBTI and PBTI. The long-term threshold voltage drifts induced by NBTI and PBTI degrade SRAM cell stability, margin, and performance, and lead to eventual functional failure. During SRAM design, it is important to build in design margins to achieve an adequate lifetime [1,2]. As this has become more challenging, several authors have proposed methods to improve SRAM reliability in the presence of NBTI/PBTI degradation. These approaches include circuitry that periodically flips the data in an SRAM cell to reduce failure rates [3], the use of redundancy [4– 6], error correcting codes [7,8], and both [9]. Evaluation of these methods requires a model of cell stress. Assumptions are usually made about the stress distribution among cells. This is because characterizing each SRAM cell based on actual operating conditions is not straightforward. The purpose of this paper is to develop the link between the device level NBTI/PBTI models and circuit performances while taking into account actual operating conditions. We demonstrate the feasibility of our methodology by presenting results from a simulator based on the proposed methodology. Since NBTI/PBTI is activity and temperature dependent, the proposed framework determines the detailed thermal profile of the memory under study, as well as the electrical stress of each of the SRAM cells within the memory. This enables a designer to make any updates in the design to enhance reliability prior to committing a design to manufacture and allows the evaluation of reliability enhance- ment techniques, such as the use of on-line reconfiguration and error correction codes (ECCs). The rest of the paper is organized as follows. Section 2 presents the device-level wearout models and circuit we used. Section 3 gives an overview of our aging assessment framework. The meth- odology to determine model parameters through FPGA emulation is also described. In Section 4, we study the impact of NBTI/PBTI on the memory under study using our simulator and present the results on performance degradation. A comparison of memory per- formance degradation analyzed with different wearout models is also presented. Section 5 concludes the paper. 2. Wearout models 2.1. NBTI/PBTI models NBTI is the degradation of a PMOS device under negative stress, and PBTI is the degradation of an NMOS device under positive stress. NBTI and PBTI result in shifts in device parameters, such as threshold voltage, transconductance, and device mobility, but are generally identified by shifts in the threshold voltage. A model of threshold voltage and its shift as a function of stress has three components. There is a model of the initial distribution, a model of the mean shift as a function of time under stress and recovery, and a model of the standard deviation of the shift, mod- eling the random variation of the change in threshold voltage for devices that experience identical stress profiles. The initial distribution is generally assumed to be Normal. Recent experimental work has shown that the threshold voltage shift as a function of time under DC stress (t DC ) is best modeled with trapping/de-trapping theory [10,11]: 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.06.003 ⇑ Corresponding author. Tel.: +1 404 894 4793; fax: +1 404 894 4641. E-mail address: linda.milor@ece.gatech.edu (L. Milor). Microelectronics Reliability xxx (2013) xxx–xxx Contents lists available at SciVerse ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel Please cite this article in press as: Chen C-C et al. Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis. Mi- croelectron Reliab (2013), http://dx.doi.org/10.1016/j.microrel.2013.06.003