Journal of Computational Electronics https://doi.org/10.1007/s10825-018-1280-z Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance Bandi Venkata Chandan 1 · Maitreyee Gautami 1 · Kaushal Nigam 2 · Dheeraj Sharma 1 · Vinay Anand Tikkiwal 2 · Shivendra Yadav 1 · Satyendra Kumar 2 © Springer Science+Business Media, LLC, part of Springer Nature 2018 Abstract To achieve a steep subthreshold slope (SS) and a better I ON / I OFF ratio is a major concern for switching applications in semiconductor devices. To overcome these issues, the tunnel field effect transistor (TFET) is a promising device, as it has low leakage current and a low subthreshold slope at room temperature, making it a highly useful device for ultra-lower circuit applications. However, physical doping leads to random doping fluctuations, which is a serious issue in device technology. For this purpose, we report an electrically doped TFET with a metal strip implanted in the oxide layer between the channel/source junction to improve the performance of the device in terms of steep SS and I ON / I OFF at very small gate voltage. Furthermore, we have considered the appropriate length and work function of the metal strip to maintain the improved SS and I ON / I OFF ratio. The introduction of a metal strip in the oxide layer on a conventional device offers a higher I ON / I OFF ratio on the order of 10 8 , steep subthreshold slope (Point SS = 8.07 mV/decade) and significant change in analog/RF performance. The analog/RF figures of merit are observed in terms of transconductance (g m ), gate-to-drain capacitance (C gd ), cutoff frequency ( f T ), and gain bandwidth product. The proposed device would be very useful for ultra-low power and high frequency circuit applications at low gate voltages. All simulated results are carried out using 2-D ATLAS software. Keywords Electrically doped TFET · Metal strip (MS) · Polarity gate (PG) · Control gate (CG) · Atlas software 1 Introduction In the era of modern technology, several alternative devices such as multi-gate, tri-gate, gate-all-around, and junctionless metal-oxide semiconductor field-effect transistors (MOS- FETS) have been studied [1–4] in order to overcome the scaling limits that cause short channel effects such as high leakage current, drain-induced barrier lowering, threshold voltage roll-off, and sub-threshold slope greater than 60 mV/decade, which degrades the device performance for ultra-low-power applications. Therefore, tunnel field effect transistors (TFETs) are promising potential candidates to overcome the aforementioned issues. They have garnered much attention in the research community, due to their merits of a sub-threshold slope less than 60 mV/dec at B Bandi Venkata Chandan venkata.chandan@gmail.com 1 PDPM-India Institute of Information Technology Design and Manufacturing, Jabalpur, M.P., India 2 Jaypee Institute of Information Technology, Noida, India 300 K and low OFF-state current [5–8]. TFET physics is based on a non-local band-to-band tunneling phenomenon at the source-channel and drain-channel junctions. Although TFETs exhibit some limitation such as inferior ON-state cur- rent and ambipolar behaviour, there are various possible ways to overcome these limitations, as can be found in the earlier literature [9–14]. However, fabrication complexity of phys- ical doped source and drain regions are major issues such as random dopant fluctuations (RDFs) [15,16] in the nano- scale regime. In this regard, the junctionless TFET has been studied in which it does need a uniform heavily N + doped sil- icon layer instead of two P-N junctions at the source/channel and channel/drain junction such as in the case of conven- tional TFETs [17,18]. But, it still generates the requirement of a complex thermal budget for expensive thermal annealing techniques and ion implantation. In this regard, doping-less TFETs have been further stud- ied using the charge plasma (CP-TFET) concept [19]. In CP-TFET, drain and source regions are formed with the appli- cation of work-function engineering. The tunneling current of CP-TFETs is better than ED-TFETs, while the analog/RF 123