IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 8, AUGUST 1998 297 Reduction of Base–Collector Capacitance in InP/InGaAs HBT’s Using a Novel Double Polyimide Planarization Process Hyunchol Shin, Christoph Gaessler, and Helmut Leier Abstract— The parasitic base–collector capacitance ( ) in InP/InGaAs heterojunction bipolar transistors (HBT’s) has been reduced using a novel double polyimide planarization process which avoids damage of the extrinsic base layer. The extrinsic base metal outside the base–collector mesa is placed on the poly- imide by polyimide coating and etch-back to the base layer. We obtained of 81 GHz and of 103 GHz with a m emitter. Performance comparison between two devices with the same area of m but with different base–collector mesa area showed 56% reduction of and 35% increase of and . Index Terms—Base–collector capacitance, InP/InGaAs HBT. I. INTRODUCTION A LOT of effort has been made in order to reduce the parasitic base–collector capacitance ( ) in HBT’s for high-speed operation. Ion implantation into the extrinsic collector region below the base layer [1] has been the most widely used method for isolation of GaAs based HBT’s. Recently, deep ion implantation [2] into the subcollector region has been proposed to remove the parasitic capacitance completely. Various methods have been reported for low- HBT structure, such as buried SiO and polycrystalline GaAs in the extrinsic base and collector [3], buried subcollector using selective epitaxy [4], triangular void using selective MOCVD [5], micro-airbridge interconnection [6], silicon nitride pla- narization [7], and undercutting the collector and subcollector layer using selective etching [8]. An interesting result has been reported by Shigematsu et al. [9]. They obtained high and with a m emitter. In order to reduce the base–collector mesa area and consequently the base–collector capacitance, they employed a combination of dummy emitter, silicon oxinitride sidewall and polyimide planarization with etch-back to the base layer level. The base metal is placed partially on the semiconductor and partially on the polyimide. Their results, however, were limited to the rather large emitter area device ( m) although the improvement should be more significant in small area devices. In this work, we develop a new process for InP/InGaAs HBT’s with reduced employing planarization with etch- back to the base layer level and base layer protection by Manuscript received January 6, 1998; revised April 7, 1998. H. Shin was with the Department of Electrical Engineering, Korea Ad- vanced Institute of Science and Technology (KAIST), Taejon 305-701, Korea. He is now with Daimler Benz Research Center, 89081 Ulm, Germany. C. Gaessler and H. Leier are with Daimler Benz Research Center, 89081 Ulm, Germany. Publisher Item Identifier S 0741-3106(98)05555-4. the emitter layer to avoid any possible process damage. The developed process is attained by changing the sequence of the base and collector metallization from the conventional poly- imide planarization process. Comparative data for m emitter devices will be presented to show the performance improvement. II. DEVICE STRUCTURE AND FABRICATION The InP/InGaAs HBT structure for this work was grown by all-solid source molecular beam epitaxy (SSMBE) [10] on 2-in semi-insulating InP substrate. The epitaxial structure consists of a 6000- ˚ An InGaAs subcollector ( cm ), 5000- ˚ A n-InGaAs collector ( cm ), 900 ˚ Ap InGaAs base (Be : cm ), 70- ˚ A i-InGaAs spacer, 600- ˚ A n-InP emitter ( cm ), 500- ˚ An InP cap ( cm ), and 1800- ˚ An InGaAs cap ( cm ). Device fabrication begins with the emitter metallization (Ti/Pt/Au). InGaAs cap layer is etched using the emitter metal as an etch mask. InP emitter and cap layer is not etched at this step to allow protection of the InGaAs base layer during the following process steps, especially during the etch-back of polyimide to the base layer level. Base–collector mesa etching is carried out down to the subcollector layer using photoresist mask. The InP layer is etched using chemically assisted ion beam etching (CAIBE) with Ar/Cl and the InGaAs collector layer is etched using phosphoric acid-based etchant (H PO :H O :H O). Wet chemical etching cannot be used for InP layer etching because the under-etching of the InP below the photoresist is extremely severe. Collector metalliza- tion and device isolation is performed. After that, polyimide is coated for the first planarization and etched back to the base layer level using O -plasma reactive ion etching (RIE) [see Fig. 1(a)]. After etch-back to the base layer, InP emitter layer is etched out by HCl-based etchant and base contact (Ti/Pt/Au) is formed [see Fig. 1(b)]. So the base layer surface is protected by the emitter layer from any possible process damage until the base metallization. Polyimide is coated again for the second planarization and etched back to the emitter metal. Finally, polyimide via is formed over the base and collector metal using RIE etching and gold electroplating is performed for interconnection metallization [see Fig. 1(c)]. III. RESULTS AND DISCUSSION The common emitter dc current gains are 51 for m emitter area and 28 for m emitter area. Large devices 0741–3106/98$10.00  1998 IEEE